Lines Matching full:enum

50 typedef enum GDS_PERFCOUNT_SELECT {
180  * GATCL1RequestType enum
183 typedef enum GATCL1RequestType {
190  * UTCL1RequestType enum
193 typedef enum UTCL1RequestType {
200  * UTCL1FaultType enum
203 typedef enum UTCL1FaultType {
211  * UTCL0RequestType enum
214 typedef enum UTCL0RequestType {
221  * UTCL0FaultType enum
224 typedef enum UTCL0FaultType {
232  * VMEMCMD_RETURN_ORDER enum
235 typedef enum VMEMCMD_RETURN_ORDER {
242  * GL0V_CACHE_POLICIES enum
245 typedef enum GL0V_CACHE_POLICIES {
253  * GL1_CACHE_POLICIES enum
256 typedef enum GL1_CACHE_POLICIES {
264  * GL1_CACHE_STORE_POLICIES enum
267 typedef enum GL1_CACHE_STORE_POLICIES {
272  * TCC_CACHE_POLICIES enum
275 typedef enum TCC_CACHE_POLICIES {
281  * TCC_MTYPE enum
284 typedef enum TCC_MTYPE {
291  * GL2_CACHE_POLICIES enum
294 typedef enum GL2_CACHE_POLICIES {
302  * MTYPE enum
305 typedef enum MTYPE {
317  * RMI_CID enum
320 typedef enum RMI_CID {
332  * WritePolicy enum
335 typedef enum WritePolicy {
343  * ReadPolicy enum
346 typedef enum ReadPolicy {
354  * PERFMON_COUNTER_MODE enum
357 typedef enum PERFMON_COUNTER_MODE {
372  * PERFMON_SPM_MODE enum
375 typedef enum PERFMON_SPM_MODE {
390  * SurfaceTiling enum
393 typedef enum SurfaceTiling {
399  * SurfaceArray enum
402 typedef enum SurfaceArray {
410  * ColorArray enum
413 typedef enum ColorArray {
420  * DepthArray enum
423 typedef enum DepthArray {
429  * ENUM_NUM_SIMD_PER_CU enum
432 typedef enum ENUM_NUM_SIMD_PER_CU {
437  * DSM_ENABLE_ERROR_INJECT enum
440 typedef enum DSM_ENABLE_ERROR_INJECT {
448  * DSM_SELECT_INJECT_DELAY enum
451 typedef enum DSM_SELECT_INJECT_DELAY {
457  * DSM_DATA_SEL enum
460 typedef enum DSM_DATA_SEL {
468  * DSM_SINGLE_WRITE enum
471 typedef enum DSM_SINGLE_WRITE {
477  * Hdp_SurfaceEndian enum
480 typedef enum Hdp_SurfaceEndian {
492  * CNVC_ENABLE enum
495 typedef enum CNVC_ENABLE {
501  * CNVC_BYPASS enum
504 typedef enum CNVC_BYPASS {
510  * CNVC_PENDING enum
513 typedef enum CNVC_PENDING {
519  * DENORM_TRUNCATE enum
522 typedef enum DENORM_TRUNCATE {
528  * PIX_EXPAND_MODE enum
531 typedef enum PIX_EXPAND_MODE {
537  * SURFACE_PIXEL_FORMAT enum
540 typedef enum SURFACE_PIXEL_FORMAT {
618  * XNORM enum
621 typedef enum XNORM {
627  * COLOR_KEYER_MODE enum
630 typedef enum COLOR_KEYER_MODE {
642  * CUR_ENABLE enum
645 typedef enum CUR_ENABLE {
651  * CUR_PENDING enum
654 typedef enum CUR_PENDING {
660  * CUR_EXPAND_MODE enum
663 typedef enum CUR_EXPAND_MODE {
669  * CUR_ROM_EN enum
672 typedef enum CUR_ROM_EN {
678  * CUR_MODE enum
681 typedef enum CUR_MODE {
691  * CUR_INV_CLAMP enum
694 typedef enum CUR_INV_CLAMP {
704  * SCL_COEF_FILTER_TYPE_SEL enum
707 typedef enum SCL_COEF_FILTER_TYPE_SEL {
717  * DSCL_MODE_SEL enum
720 typedef enum DSCL_MODE_SEL {
731  * SCL_AUTOCAL_MODE enum
734 typedef enum SCL_AUTOCAL_MODE {
742  * SCL_COEF_RAM_SEL enum
745 typedef enum SCL_COEF_RAM_SEL {
751  * SCL_CHROMA_COEF enum
754 typedef enum SCL_CHROMA_COEF {
760  * SCL_ALPHA_COEF enum
763 typedef enum SCL_ALPHA_COEF {
769  * COEF_RAM_SELECT_RD enum
772 typedef enum COEF_RAM_SELECT_RD {
778  * SCL_2TAP_HARDCODE enum
781 typedef enum SCL_2TAP_HARDCODE {
787  * SCL_SHARP_EN enum
790 typedef enum SCL_SHARP_EN {
796  * SCL_BOUNDARY enum
799 typedef enum SCL_BOUNDARY {
805  * LB_INTERLEAVE_EN enum
808 typedef enum LB_INTERLEAVE_EN {
814  * LB_ALPHA_EN enum
817 typedef enum LB_ALPHA_EN {
823  * OBUF_BYPASS_SEL enum
826 typedef enum OBUF_BYPASS_SEL {
832  * OBUF_USE_FULL_BUFFER_SEL enum
835 typedef enum OBUF_USE_FULL_BUFFER_SEL {
841  * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
844 typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
854  * CM_BYPASS enum
857 typedef enum CM_BYPASS {
863  * CM_EN enum
866 typedef enum CM_EN {
872  * CM_PENDING enum
875 typedef enum CM_PENDING {
881  * CM_DATA_SIGNED enum
884 typedef enum CM_DATA_SIGNED {
890  * CM_WRITE_BASE_ONLY enum
893 typedef enum CM_WRITE_BASE_ONLY {
899  * CM_LUT_4_CONFIG_ENUM enum
902 typedef enum CM_LUT_4_CONFIG_ENUM {
911  * CM_LUT_2_CONFIG_ENUM enum
914 typedef enum CM_LUT_2_CONFIG_ENUM {
921  * CM_LUT_4_MODE_ENUM enum
924 typedef enum CM_LUT_4_MODE_ENUM {
933  * CM_LUT_2_MODE_ENUM enum
936 typedef enum CM_LUT_2_MODE_ENUM {
943  * CM_LUT_RAM_SEL enum
946 typedef enum CM_LUT_RAM_SEL {
952  * CM_LUT_NUM_SEG enum
955 typedef enum CM_LUT_NUM_SEG {
967  * CM_ICSC_MODE_ENUM enum
970 typedef enum CM_ICSC_MODE_ENUM {
977  * CM_GAMUT_REMAP_MODE_ENUM enum
980 typedef enum CM_GAMUT_REMAP_MODE_ENUM {
987  * CM_COEF_FORMAT_ENUM enum
990 typedef enum CM_COEF_FORMAT_ENUM {
996  * CMC_LUT_2_CONFIG_ENUM enum
999 typedef enum CMC_LUT_2_CONFIG_ENUM {
1006  * CMC_LUT_2_MODE_ENUM enum
1009 typedef enum CMC_LUT_2_MODE_ENUM {
1016  * CMC_LUT_RAM_SEL enum
1019 typedef enum CMC_LUT_RAM_SEL {
1025  * CMC_3DLUT_RAM_SEL enum
1028 typedef enum CMC_3DLUT_RAM_SEL {
1036  * CMC_LUT_NUM_SEG enum
1039 typedef enum CMC_LUT_NUM_SEG {
1051  * CMC_3DLUT_30BIT_ENUM enum
1054 typedef enum CMC_3DLUT_30BIT_ENUM {
1060  * CMC_3DLUT_SIZE_ENUM enum
1063 typedef enum CMC_3DLUT_SIZE_ENUM {
1073  * TEST_CLK_SEL enum
1076 typedef enum TEST_CLK_SEL {
1089  * CRC_SRC_SEL enum
1092 typedef enum CRC_SRC_SEL {
1100  * CRC_IN_PIX_SEL enum
1103 typedef enum CRC_IN_PIX_SEL {
1115  * CRC_CUR_BITS_SEL enum
1118 typedef enum CRC_CUR_BITS_SEL {
1124  * CRC_IN_CUR_SEL enum
1127 typedef enum CRC_IN_CUR_SEL {
1133  * CRC_CUR_SEL enum
1136 typedef enum CRC_CUR_SEL {
1142  * CRC_STEREO_SEL enum
1145 typedef enum CRC_STEREO_SEL {
1153  * CRC_INTERLACE_SEL enum
1156 typedef enum CRC_INTERLACE_SEL {
1168  * PERFCOUNTER_CVALUE_SEL enum
1171 typedef enum PERFCOUNTER_CVALUE_SEL {
1183  * PERFCOUNTER_INC_MODE enum
1186 typedef enum PERFCOUNTER_INC_MODE {
1195  * PERFCOUNTER_HW_CNTL_SEL enum
1198 typedef enum PERFCOUNTER_HW_CNTL_SEL {
1204  * PERFCOUNTER_RUNEN_MODE enum
1207 typedef enum PERFCOUNTER_RUNEN_MODE {
1213  * PERFCOUNTER_CNTOFF_START_DIS enum
1216 typedef enum PERFCOUNTER_CNTOFF_START_DIS {
1222  * PERFCOUNTER_RESTART_EN enum
1225 typedef enum PERFCOUNTER_RESTART_EN {
1231  * PERFCOUNTER_INT_EN enum
1234 typedef enum PERFCOUNTER_INT_EN {
1240  * PERFCOUNTER_OFF_MASK enum
1243 typedef enum PERFCOUNTER_OFF_MASK {
1249  * PERFCOUNTER_ACTIVE enum
1252 typedef enum PERFCOUNTER_ACTIVE {
1258  * PERFCOUNTER_INT_TYPE enum
1261 typedef enum PERFCOUNTER_INT_TYPE {
1267  * PERFCOUNTER_COUNTED_VALUE_TYPE enum
1270 typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
1277  * PERFCOUNTER_HW_STOP1_SEL enum
1280 typedef enum PERFCOUNTER_HW_STOP1_SEL {
1286  * PERFCOUNTER_HW_STOP2_SEL enum
1289 typedef enum PERFCOUNTER_HW_STOP2_SEL {
1295  * PERFCOUNTER_CNTL_SEL enum
1298 typedef enum PERFCOUNTER_CNTL_SEL {
1310  * PERFCOUNTER_CNT0_STATE enum
1313 typedef enum PERFCOUNTER_CNT0_STATE {
1321  * PERFCOUNTER_STATE_SEL0 enum
1324 typedef enum PERFCOUNTER_STATE_SEL0 {
1330  * PERFCOUNTER_CNT1_STATE enum
1333 typedef enum PERFCOUNTER_CNT1_STATE {
1341  * PERFCOUNTER_STATE_SEL1 enum
1344 typedef enum PERFCOUNTER_STATE_SEL1 {
1350  * PERFCOUNTER_CNT2_STATE enum
1353 typedef enum PERFCOUNTER_CNT2_STATE {
1361  * PERFCOUNTER_STATE_SEL2 enum
1364 typedef enum PERFCOUNTER_STATE_SEL2 {
1370  * PERFCOUNTER_CNT3_STATE enum
1373 typedef enum PERFCOUNTER_CNT3_STATE {
1381  * PERFCOUNTER_STATE_SEL3 enum
1384 typedef enum PERFCOUNTER_STATE_SEL3 {
1390  * PERFCOUNTER_CNT4_STATE enum
1393 typedef enum PERFCOUNTER_CNT4_STATE {
1401  * PERFCOUNTER_STATE_SEL4 enum
1404 typedef enum PERFCOUNTER_STATE_SEL4 {
1410  * PERFCOUNTER_CNT5_STATE enum
1413 typedef enum PERFCOUNTER_CNT5_STATE {
1421  * PERFCOUNTER_STATE_SEL5 enum
1424 typedef enum PERFCOUNTER_STATE_SEL5 {
1430  * PERFCOUNTER_CNT6_STATE enum
1433 typedef enum PERFCOUNTER_CNT6_STATE {
1441  * PERFCOUNTER_STATE_SEL6 enum
1444 typedef enum PERFCOUNTER_STATE_SEL6 {
1450  * PERFCOUNTER_CNT7_STATE enum
1453 typedef enum PERFCOUNTER_CNT7_STATE {
1461  * PERFCOUNTER_STATE_SEL7 enum
1464 typedef enum PERFCOUNTER_STATE_SEL7 {
1470  * PERFMON_STATE enum
1473 typedef enum PERFMON_STATE {
1481  * PERFMON_CNTOFF_AND_OR enum
1484 typedef enum PERFMON_CNTOFF_AND_OR {
1490  * PERFMON_CNTOFF_INT_EN enum
1493 typedef enum PERFMON_CNTOFF_INT_EN {
1499  * PERFMON_CNTOFF_INT_TYPE enum
1502 typedef enum PERFMON_CNTOFF_INT_TYPE {
1512  * ROTATION_ANGLE enum
1515 typedef enum ROTATION_ANGLE {
1523  * H_MIRROR_EN enum
1526 typedef enum H_MIRROR_EN {
1532  * NUM_PIPES enum
1535 typedef enum NUM_PIPES {
1546  * NUM_BANKS enum
1549 typedef enum NUM_BANKS {
1558  * SW_MODE enum
1561 typedef enum SW_MODE {
1581  * PIPE_INTERLEAVE enum
1584 typedef enum PIPE_INTERLEAVE {
1591  * LEGACY_PIPE_INTERLEAVE enum
1594 typedef enum LEGACY_PIPE_INTERLEAVE {
1600  * NUM_SE enum
1603 typedef enum NUM_SE {
1611  * NUM_RB_PER_SE enum
1614 typedef enum NUM_RB_PER_SE {
1621  * MAX_COMPRESSED_FRAGS enum
1624 typedef enum MAX_COMPRESSED_FRAGS {
1632  * DIM_TYPE enum
1635 typedef enum DIM_TYPE {
1643  * META_LINEAR enum
1646 typedef enum META_LINEAR {
1652  * RB_ALIGNED enum
1655 typedef enum RB_ALIGNED {
1661  * PIPE_ALIGNED enum
1664 typedef enum PIPE_ALIGNED {
1670  * ARRAY_MODE enum
1673 typedef enum ARRAY_MODE {
1693  * PIPE_CONFIG enum
1696 typedef enum PIPE_CONFIG {
1715  * MICRO_TILE_MODE_NEW enum
1718 typedef enum MICRO_TILE_MODE_NEW {
1727  * TILE_SPLIT enum
1730 typedef enum TILE_SPLIT {
1741  * BANK_WIDTH enum
1744 typedef enum BANK_WIDTH {
1752  * BANK_HEIGHT enum
1755 typedef enum BANK_HEIGHT {
1763  * MACRO_TILE_ASPECT enum
1766 typedef enum MACRO_TILE_ASPECT {
1774  * LEGACY_NUM_BANKS enum
1777 typedef enum LEGACY_NUM_BANKS {
1785  * SWATH_HEIGHT enum
1788 typedef enum SWATH_HEIGHT {
1797  * PTE_ROW_HEIGHT_LINEAR enum
1800 typedef enum PTE_ROW_HEIGHT_LINEAR {
1812  * CHUNK_SIZE enum
1815 typedef enum CHUNK_SIZE {
1826  * MIN_CHUNK_SIZE enum
1829 typedef enum MIN_CHUNK_SIZE {
1837  * META_CHUNK_SIZE enum
1840 typedef enum META_CHUNK_SIZE {
1848  * MIN_META_CHUNK_SIZE enum
1851 typedef enum MIN_META_CHUNK_SIZE {
1859  * DPTE_GROUP_SIZE enum
1862 typedef enum DPTE_GROUP_SIZE {
1874  * MPTE_GROUP_SIZE enum
1877 typedef enum MPTE_GROUP_SIZE {
1889  * HUBP_BLANK_EN enum
1892 typedef enum HUBP_BLANK_EN {
1898  * HUBP_DISABLE enum
1901 typedef enum HUBP_DISABLE {
1907  * HUBP_TTU_DISABLE enum
1910 typedef enum HUBP_TTU_DISABLE {
1916  * HUBP_NO_OUTSTANDING_REQ enum
1919 typedef enum HUBP_NO_OUTSTANDING_REQ {
1925  * HUBP_IN_BLANK enum
1928 typedef enum HUBP_IN_BLANK {
1934  * HUBP_VTG_SEL enum
1937 typedef enum HUBP_VTG_SEL {
1947  * HUBP_VREADY_AT_OR_AFTER_VSYNC enum
1950 typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
1956  * VMPG_SIZE enum
1959 typedef enum VMPG_SIZE {
1965  * HUBP_MEASURE_WIN_MODE_DCFCLK enum
1968 typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
1980  * SURFACE_TMZ enum
1983 typedef enum SURFACE_TMZ {
1989  * SURFACE_DCC enum
1992 typedef enum SURFACE_DCC {
1998  * SURFACE_DCC_IND_64B enum
2001 typedef enum SURFACE_DCC_IND_64B {
2007  * SURFACE_FLIP_TYPE enum
2010 typedef enum SURFACE_FLIP_TYPE {
2016  * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum
2019 typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC {
2027  * SURFACE_UPDATE_LOCK enum
2030 typedef enum SURFACE_UPDATE_LOCK {
2036  * SURFACE_FLIP_IN_STEREOSYNC enum
2039 typedef enum SURFACE_FLIP_IN_STEREOSYNC {
2045  * SURFACE_FLIP_STEREO_SELECT_DISABLE enum
2048 typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE {
2054  * SURFACE_FLIP_STEREO_SELECT_POLARITY enum
2057 typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY {
2063  * SURFACE_INUSE_RAED_NO_LATCH enum
2066 typedef enum SURFACE_INUSE_RAED_NO_LATCH {
2072  * INT_MASK enum
2075 typedef enum INT_MASK {
2081  * SURFACE_FLIP_INT_TYPE enum
2084 typedef enum SURFACE_FLIP_INT_TYPE {
2090  * SURFACE_FLIP_AWAY_INT_TYPE enum
2093 typedef enum SURFACE_FLIP_AWAY_INT_TYPE {
2099  * SURFACE_FLIP_VUPDATE_SKIP_NUM enum
2102 typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM {
2122  * DFQ_SIZE enum
2125 typedef enum DFQ_SIZE {
2137  * DFQ_MIN_FREE_ENTRIES enum
2140 typedef enum DFQ_MIN_FREE_ENTRIES {
2152  * DFQ_NUM_ENTRIES enum
2155 typedef enum DFQ_NUM_ENTRIES {
2168  * FLIP_RATE enum
2171 typedef enum FLIP_RATE {
2187  * DETILE_BUFFER_PACKER_ENABLE enum
2190 typedef enum DETILE_BUFFER_PACKER_ENABLE {
2196  * CROSSBAR_FOR_ALPHA enum
2199 typedef enum CROSSBAR_FOR_ALPHA {
2207  * CROSSBAR_FOR_Y_G enum
2210 typedef enum CROSSBAR_FOR_Y_G {
2218  * CROSSBAR_FOR_CB_B enum
2221 typedef enum CROSSBAR_FOR_CB_B {
2229  * CROSSBAR_FOR_CR_R enum
2232 typedef enum CROSSBAR_FOR_CR_R {
2240  * DET_MEM_PWR_LIGHT_SLEEP_MODE enum
2243 typedef enum DET_MEM_PWR_LIGHT_SLEEP_MODE {
2250  * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum
2253 typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE {
2263  * CURSOR_ENABLE enum
2266 typedef enum CURSOR_ENABLE {
2272  * CURSOR_2X_MAGNIFY enum
2275 typedef enum CURSOR_2X_MAGNIFY {
2281  * CURSOR_MODE enum
2284 typedef enum CURSOR_MODE {
2294  * CURSOR_SURFACE_TMZ enum
2297 typedef enum CURSOR_SURFACE_TMZ {
2303  * CURSOR_SNOOP enum
2306 typedef enum CURSOR_SNOOP {
2312  * CURSOR_SYSTEM enum
2315 typedef enum CURSOR_SYSTEM {
2321  * CURSOR_PITCH enum
2324 typedef enum CURSOR_PITCH {
2331  * CURSOR_LINES_PER_CHUNK enum
2334 typedef enum CURSOR_LINES_PER_CHUNK {
2343  * CURSOR_PERFMON_LATENCY_MEASURE_EN enum
2346 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN {
2352  * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum
2355 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL {
2361  * CURSOR_STEREO_EN enum
2364 typedef enum CURSOR_STEREO_EN {
2370  * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum
2373 typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS {
2379  * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum
2382 typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE {
2389  * DMDATA_UPDATED enum
2392 typedef enum DMDATA_UPDATED {
2398  * DMDATA_REPEAT enum
2401 typedef enum DMDATA_REPEAT {
2407  * DMDATA_MODE enum
2410 typedef enum DMDATA_MODE {
2416  * DMDATA_QOS_MODE enum
2419 typedef enum DMDATA_QOS_MODE {
2425  * DMDATA_DONE enum
2428 typedef enum DMDATA_DONE {
2434  * DMDATA_UNDERFLOW enum
2437 typedef enum DMDATA_UNDERFLOW {
2443  * DMDATA_UNDERFLOW_CLEAR enum
2446 typedef enum DMDATA_UNDERFLOW_CLEAR {
2456  * HUBP_XFC_PIXEL_FORMAT_ENUM enum
2459 typedef enum HUBP_XFC_PIXEL_FORMAT_ENUM {
2465  * HUBP_XFC_FRAME_MODE_ENUM enum
2468 typedef enum HUBP_XFC_FRAME_MODE_ENUM {
2474  * HUBP_XFC_CHUNK_SIZE_ENUM enum
2477 typedef enum HUBP_XFC_CHUNK_SIZE_ENUM {
2493  * MMHUBBUB_XFC_XFCMON_MODE_ENUM enum
2496 typedef enum MMHUBBUB_XFC_XFCMON_MODE_ENUM {
2503  * MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM enum
2506 typedef enum MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM {
2516  * MMHUBBUB_XFC_PIXEL_FORMAT_ENUM enum
2519 typedef enum MMHUBBUB_XFC_PIXEL_FORMAT_ENUM {
2525  * MMHUBBUB_XFC_FRAME_MODE_ENUM enum
2528 typedef enum MMHUBBUB_XFC_FRAME_MODE_ENUM {
2538  * MPC_CFG_MPC_TEST_CLK_SEL enum
2541 typedef enum MPC_CFG_MPC_TEST_CLK_SEL {
2549  * MPC_CRC_CALC_MODE enum
2552 typedef enum MPC_CRC_CALC_MODE {
2558  * MPC_CRC_CALC_STEREO_MODE enum
2561 typedef enum MPC_CRC_CALC_STEREO_MODE {
2569  * MPC_CRC_CALC_INTERLACE_MODE enum
2572 typedef enum MPC_CRC_CALC_INTERLACE_MODE {
2580  * MPC_CRC_SOURCE_SELECT enum
2583 typedef enum MPC_CRC_SOURCE_SELECT {
2591  * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum
2594 typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET {
2600  * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum
2603 typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET {
2609  * MPC_CFG_CFG_VUPDATE_LOCK_SET enum
2612 typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET {
2618  * MPC_CFG_ADR_VUPDATE_LOCK_SET enum
2621 typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET {
2627  * MPC_CFG_CUR_VUPDATE_LOCK_SET enum
2630 typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET {
2636  * MPC_OUT_RATE_CONTROL_DISABLE_SET enum
2639 typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET {
2645  * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum
2648 typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE {
2664  * MPC_OCSC_COEF_FORMAT enum
2667 typedef enum MPC_OCSC_COEF_FORMAT {
2673  * MPC_OUT_CSC_MODE enum
2676 typedef enum MPC_OUT_CSC_MODE {
2688  * MPCC_CONTROL_MPCC_MODE enum
2691 typedef enum MPCC_CONTROL_MPCC_MODE {
2699  * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum
2702 typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE {
2710  * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum
2713 typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE {
2719  * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum
2722 typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY {
2728  * MPCC_SM_CONTROL_MPCC_SM_EN enum
2731 typedef enum MPCC_SM_CONTROL_MPCC_SM_EN {
2737  * MPCC_SM_CONTROL_MPCC_SM_MODE enum
2740 typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE {
2748  * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum
2751 typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT {
2757  * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum
2760 typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT {
2766  * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum
2769 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL {
2777  * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum
2780 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL {
2788  * MPCC_STALL_STATUS_MPCC_STALL_INT_ACK enum
2791 typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_ACK {
2797  * MPCC_STALL_STATUS_MPCC_STALL_INT_MASK enum
2800 typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_MASK {
2806  * MPCC_BG_COLOR_BPC enum
2809 typedef enum MPCC_BG_COLOR_BPC {
2818  * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum
2821 typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE {
2831  * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum
2834 typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL {
2840  * MPCC_OGAM_MODE_MPCC_OGAM_MODE enum
2843 typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE {
2855  * ENUM_DPG_EN enum
2858 typedef enum ENUM_DPG_EN {
2864  * ENUM_DPG_MODE enum
2867 typedef enum ENUM_DPG_MODE {
2879  * ENUM_DPG_DYNAMIC_RANGE enum
2882 typedef enum ENUM_DPG_DYNAMIC_RANGE {
2888  * ENUM_DPG_BIT_DEPTH enum
2891 typedef enum ENUM_DPG_BIT_DEPTH {
2899  * ENUM_DPG_FIELD_POLARITY enum
2902 typedef enum ENUM_DPG_FIELD_POLARITY {
2912  * FMT_CONTROL_PIXEL_ENCODING enum
2915 typedef enum FMT_CONTROL_PIXEL_ENCODING {
2923  * FMT_CONTROL_SUBSAMPLING_MODE enum
2926 typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
2934  * FMT_CONTROL_SUBSAMPLING_ORDER enum
2937 typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
2943  * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
2946 typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
2952  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
2955 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
2961  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
2964 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
2971  * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
2974 typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
2981  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
2984 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
2991  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
2994 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3000  * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3003 typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3011  * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3014 typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3022  * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3025 typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3033  * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3036 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3042  * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3045 typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3057  * FMT_SPATIAL_DITHER_MODE enum
3060 typedef enum FMT_SPATIAL_DITHER_MODE {
3068  * FMT_DYNAMIC_EXP_MODE enum
3071 typedef enum FMT_DYNAMIC_EXP_MODE {
3077  * FMTMEM_PWR_FORCE_CTRL enum
3080 typedef enum FMTMEM_PWR_FORCE_CTRL {
3088  * FMTMEM_PWR_DIS_CTRL enum
3091 typedef enum FMTMEM_PWR_DIS_CTRL {
3097  * FMT_POWER_STATE_ENUM enum
3100 typedef enum FMT_POWER_STATE_ENUM {
3108  * FMT_STEREOSYNC_OVERRIDE_CONTROL enum
3111 typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL {
3117  * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum
3120 typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL {
3128  * FMT_FRAME_RANDOM_ENABLE_CONTROL enum
3131 typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL {
3137  * FMT_RGB_RANDOM_ENABLE_CONTROL enum
3140 typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL {
3146  * ENUM_FMT_PTI_FIELD_POLARITY enum
3149 typedef enum ENUM_FMT_PTI_FIELD_POLARITY {
3159  * OPP_PIPE_CLOCK_ENABLE_CONTROL enum
3162 typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL {
3168  * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum
3171 typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL {
3181  * OPP_PIPE_CRC_EN enum
3184 typedef enum OPP_PIPE_CRC_EN {
3190  * OPP_PIPE_CRC_CONT_EN enum
3193 typedef enum OPP_PIPE_CRC_CONT_EN {
3199  * OPP_PIPE_CRC_STEREO_MODE enum
3202 typedef enum OPP_PIPE_CRC_STEREO_MODE {
3210  * OPP_PIPE_CRC_STEREO_EN enum
3213 typedef enum OPP_PIPE_CRC_STEREO_EN {
3219  * OPP_PIPE_CRC_INTERLACE_MODE enum
3222 typedef enum OPP_PIPE_CRC_INTERLACE_MODE {
3230  * OPP_PIPE_CRC_INTERLACE_EN enum
3233 typedef enum OPP_PIPE_CRC_INTERLACE_EN {
3239  * OPP_PIPE_CRC_PIXEL_SELECT enum
3242 typedef enum OPP_PIPE_CRC_PIXEL_SELECT {
3250  * OPP_PIPE_CRC_SOURCE_SELECT enum
3253 typedef enum OPP_PIPE_CRC_SOURCE_SELECT {
3259  * OPP_PIPE_CRC_ONE_SHOT_PENDING enum
3262 typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING {
3272  * OPP_TOP_CLOCK_GATING_CONTROL enum
3275 typedef enum OPP_TOP_CLOCK_GATING_CONTROL {
3281  * OPP_TOP_CLOCK_ENABLE_STATUS enum
3284 typedef enum OPP_TOP_CLOCK_ENABLE_STATUS {
3290  * OPP_TEST_CLK_SEL_CONTROL enum
3293 typedef enum OPP_TEST_CLK_SEL_CONTROL {
3311  * OTG_CONTROL_OTG_START_POINT_CNTL enum
3314 typedef enum OTG_CONTROL_OTG_START_POINT_CNTL {
3320  * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum
3323 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL {
3329  * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum
3332 typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL {
3340  * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum
3343 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY {
3349  * OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE enum
3352 typedef enum OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE {
3358  * OTG_CONTROL_OTG_SOF_PULL_EN enum
3361 typedef enum OTG_CONTROL_OTG_SOF_PULL_EN {
3367  * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum
3370 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL {
3376  * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum
3379 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL {
3385  * OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN enum
3388 typedef enum OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN {
3394  * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum
3397 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC {
3403  * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum
3406 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT {
3412  * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum
3415 typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD {
3421  * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
3424 typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
3430  * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum
3433 typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR {
3439  * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum
3442 typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN {
3448  * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum
3451 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT {
3480  * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum
3483 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT {
3495  * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum
3498 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT {
3527  * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum
3530 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT {
3540  * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum
3543 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT {
3555  * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum
3558 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT {
3568  * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum
3571 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN {
3577  * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum
3580 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR {
3586  * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum
3589 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN {
3595  * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum
3598 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR {
3604  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum
3607 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE {
3615  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum
3618 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK {
3624  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum
3627 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL {
3633  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum
3636 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR {
3642  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum
3645 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT {
3669  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum
3672 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY {
3678  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum
3681 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY {
3687  * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum
3690 typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE {
3698  * OTG_CONTROL_OTG_MASTER_EN enum
3701 typedef enum OTG_CONTROL_OTG_MASTER_EN {
3707  * OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN enum
3710 typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN {
3716  * OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE enum
3719 typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE {
3725  * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum
3728 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE {
3734  * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum
3737 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD {
3745  * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY enum
3748 typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY {
3754  * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT enum
3757 typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT {
3763  * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum
3766 typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN {
3772  * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum
3775 typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE {
3781  * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum
3784 typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR {
3790  * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum
3793 typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE {
3801  * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum
3804 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY {
3810  * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum
3813 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY {
3819  * OTG_STEREO_CONTROL_OTG_STEREO_EN enum
3822 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN {
3828  * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum
3831 typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR {
3837  * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum
3840 typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL {
3848  * OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY enum
3851 typedef enum OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY {
3857  * OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY enum
3860 typedef enum OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY {
3866  * OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN enum
3869 typedef enum OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN {
3875  * OTG_START_LINE_CONTROL_OTG_PREFETCH_EN enum
3878 typedef enum OTG_START_LINE_CONTROL_OTG_PREFETCH_EN {
3884  * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum
3887 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK {
3893  * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum
3896 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE {
3902  * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK enum
3905 typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK {
3911  * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE enum
3914 typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE {
3920  * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum
3923 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK {
3929  * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum
3932 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE {
3938  * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
3941 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK {
3947  * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
3950 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
3956  * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum
3959 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK {
3965  * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum
3968 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE {
3974  * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum
3977 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK {
3983  * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum
3986 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE {
3992  * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum
3995 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK {
4001  * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum
4004 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE {
4010  * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum
4013 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK {
4019  * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum
4022 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE {
4028  * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum
4031 typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK {
4037  * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum
4040 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY {
4046  * OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN enum
4049 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN {
4055  * OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE enum
4058 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE {
4066  * OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE enum
4069 typedef enum OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE {
4075  * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
4078 typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
4084  * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum
4087 typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME {
4095  * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
4098 typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
4104  * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
4107 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
4115  * OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE enum
4118 typedef enum OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE {
4125  * OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR enum
4128 typedef enum OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR {
4134  * OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR enum
4137 typedef enum OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR {
4143  * OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR enum
4146 typedef enum OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR {
4152  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
4155 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
4161  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum
4164 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE {
4170  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum
4173 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR {
4179  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum
4182 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE {
4188  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum
4191 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR {
4197  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum
4200 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE {
4206  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum
4209 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE {
4215  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum
4218 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR {
4224  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum
4227 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE {
4233  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum
4236 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE {
4242  * OTG_CRC_CNTL_OTG_CRC_EN enum
4245 typedef enum OTG_CRC_CNTL_OTG_CRC_EN {
4251  * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum
4254 typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN {
4260  * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum
4263 typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE {
4271  * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum
4274 typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE {
4282  * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum
4285 typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS {
4291  * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum
4294 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT {
4306  * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum
4309 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT {
4321  * OTG_CRC_CNTL2_OTG_CRC_DSC_MODE enum
4324 typedef enum OTG_CRC_CNTL2_OTG_CRC_DSC_MODE {
4330  * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE enum
4333 typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE {
4339  * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE enum
4342 typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE {
4350  * OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT enum
4353 typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT {
4361  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE enum
4364 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE {
4372  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
4375 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
4381  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
4384 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
4390  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
4393 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
4401  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE enum
4404 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE {
4410  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE enum
4413 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE {
4419  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY enum
4422 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY {
4428  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY enum
4431 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY {
4437  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE enum
4440 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE {
4446  * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
4449 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
4455  * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR enum
4458 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR {
4464  * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
4467 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE {
4473  * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
4476 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
4488  * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE enum
4491 typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE {
4497  * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR enum
4500 typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR {
4506  * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE enum
4509 typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE {
4515  * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
4518 typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
4524  * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
4527 typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR {
4533  * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
4536 typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
4542  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum
4545 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE {
4551  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum
4554 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR {
4560  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum
4563 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE {
4569  * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum
4572 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE {
4578  * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum
4581 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE {
4587  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum
4590 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN {
4596  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum
4599 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB {
4605  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum
4608 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE {
4616  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum
4619 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR {
4625  * OTG_V_SYNC_A_POL enum
4628 typedef enum OTG_V_SYNC_A_POL {
4634  * OTG_H_SYNC_A_POL enum
4637 typedef enum OTG_H_SYNC_A_POL {
4643  * OTG_HORZ_REPETITION_COUNT enum
4646 typedef enum OTG_HORZ_REPETITION_COUNT {
4666  * MASTER_UPDATE_LOCK_SEL enum
4669 typedef enum MASTER_UPDATE_LOCK_SEL {
4679  * DRR_UPDATE_LOCK_SEL enum
4682 typedef enum DRR_UPDATE_LOCK_SEL {
4692  * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum
4695 typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL {
4705  * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum
4708 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD {
4715  * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum
4718 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL {
4726  * OTG_H_TIMING_DIV_BY2 enum
4729 typedef enum OTG_H_TIMING_DIV_BY2 {
4735  * OTG_H_TIMING_DIV_BY2_UPDATE_MODE enum
4738 typedef enum OTG_H_TIMING_DIV_BY2_UPDATE_MODE {
4744  * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum
4747 typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL {
4755  * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum
4758 typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL {
4766  * OTG_TRIGA_FREQUENCY_SELECT enum
4769 typedef enum OTG_TRIGA_FREQUENCY_SELECT {
4777  * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum
4780 typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL {
4788  * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum
4791 typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL {
4799  * OTG_TRIGB_FREQUENCY_SELECT enum
4802 typedef enum OTG_TRIGB_FREQUENCY_SELECT {
4810  * OTG_PIPE_ABORT enum
4813 typedef enum OTG_PIPE_ABORT {
4819  * OTG_MASTER_UPDATE_LOCK_GSL_EN enum
4822 typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN {
4828  * OTG_PTI_CONTROL_OTG_PIT_EN enum
4831 typedef enum OTG_PTI_CONTROL_OTG_PIT_EN {
4837  * OTG_GSL_MASTER_MODE enum
4840 typedef enum OTG_GSL_MASTER_MODE {
4852  * DC_DMCUB_TIMER_WINDOW enum
4855 typedef enum DC_DMCUB_TIMER_WINDOW {
4867  * DC_DMCUB_INT_TYPE enum
4870 typedef enum DC_DMCUB_INT_TYPE {
4880  * INVALID_REG_ACCESS_TYPE enum
4883 typedef enum INVALID_REG_ACCESS_TYPE {
4895  * DMU_DC_GPU_TIMER_START_POSITION enum
4898 typedef enum DMU_DC_GPU_TIMER_START_POSITION {
4910  * DMU_DC_GPU_TIMER_READ_SELECT enum
4913 typedef enum DMU_DC_GPU_TIMER_READ_SELECT {
5009  * IHC_INTERRUPT_LINE_STATUS enum
5012 typedef enum IHC_INTERRUPT_LINE_STATUS {
5022  * DMU_CLOCK_GATING_DISABLE enum
5025 typedef enum DMU_CLOCK_GATING_DISABLE {
5031  * DMU_CLOCK_ON enum
5034 typedef enum DMU_CLOCK_ON {
5040  * DC_SMU_INTERRUPT_ENABLE enum
5043 typedef enum DC_SMU_INTERRUPT_ENABLE {
5049  * STATIC_SCREEN_SMU_INTR enum
5052 typedef enum STATIC_SCREEN_SMU_INTR {
5062  * ENABLE enum
5065 typedef enum ENABLE {
5071  * DS_HW_CAL_ENABLE enum
5074 typedef enum DS_HW_CAL_ENABLE {
5080  * ENABLE_CLOCK enum
5083 typedef enum ENABLE_CLOCK {
5089  * CLEAR_SMU_INTR enum
5092 typedef enum CLEAR_SMU_INTR {
5098  * JITTER_REMOVE_DISABLE enum
5101 typedef enum JITTER_REMOVE_DISABLE {
5107  * DS_REF_SRC enum
5110 typedef enum DS_REF_SRC {
5117  * DISABLE_CLOCK_GATING enum
5120 typedef enum DISABLE_CLOCK_GATING {
5126  * DISABLE_CLOCK_GATING_IN_DCO enum
5129 typedef enum DISABLE_CLOCK_GATING_IN_DCO {
5135  * DCCG_DEEP_COLOR_CNTL enum
5138 typedef enum DCCG_DEEP_COLOR_CNTL {
5146  * REFCLK_CLOCK_EN enum
5149 typedef enum REFCLK_CLOCK_EN {
5155  * REFCLK_SRC_SEL enum
5158 typedef enum REFCLK_SRC_SEL {
5164  * DPREFCLK_SRC_SEL enum
5167 typedef enum DPREFCLK_SRC_SEL {
5175  * XTAL_REF_SEL enum
5178 typedef enum XTAL_REF_SEL {
5184  * XTAL_REF_CLOCK_SOURCE_SEL enum
5187 typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
5193  * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5196 typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5202  * ALLOW_SR_ON_TRANS_REQ enum
5205 typedef enum ALLOW_SR_ON_TRANS_REQ {
5211  * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5214 typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5220  * PIPE_PIXEL_RATE_SOURCE enum
5223 typedef enum PIPE_PIXEL_RATE_SOURCE {
5230  * TEST_CLK_DIV_SEL enum
5233 typedef enum TEST_CLK_DIV_SEL {
5241  * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
5244 typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
5255  * PIPE_PIXEL_RATE_PLL_SOURCE enum
5258 typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
5264  * DP_DTO_DS_DISABLE enum
5267 typedef enum DP_DTO_DS_DISABLE {
5273  * OTG_ADD_PIXEL enum
5276 typedef enum OTG_ADD_PIXEL {
5282  * OTG_DROP_PIXEL enum
5285 typedef enum OTG_DROP_PIXEL {
5291  * SYMCLK_FE_FORCE_EN enum
5294 typedef enum SYMCLK_FE_FORCE_EN {
5300  * SYMCLK_FE_FORCE_SRC enum
5303 typedef enum SYMCLK_FE_FORCE_SRC {
5314  * DVOACLK_COARSE_SKEW_CNTL enum
5317 typedef enum DVOACLK_COARSE_SKEW_CNTL {
5352  * DVOACLK_FINE_SKEW_CNTL enum
5355 typedef enum DVOACLK_FINE_SKEW_CNTL {
5367  * DVOACLKD_IN_PHASE enum
5370 typedef enum DVOACLKD_IN_PHASE {
5376  * DVOACLKC_IN_PHASE enum
5379 typedef enum DVOACLKC_IN_PHASE {
5385  * DVOACLKC_MVP_IN_PHASE enum
5388 typedef enum DVOACLKC_MVP_IN_PHASE {
5394  * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
5397 typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
5403  * DCCG_AUDIO_DTO0_SOURCE_SEL enum
5406 typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
5417  * DCCG_AUDIO_DTO_SEL enum
5420 typedef enum DCCG_AUDIO_DTO_SEL {
5427  * DCCG_AUDIO_DTO2_SOURCE_SEL enum
5430 typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
5436  * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
5439 typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
5445  * DISPCLK_FREQ_RAMP_DONE enum
5448 typedef enum DISPCLK_FREQ_RAMP_DONE {
5454  * DCCG_FIFO_ERRDET_RESET enum
5457 typedef enum DCCG_FIFO_ERRDET_RESET {
5463  * DCCG_FIFO_ERRDET_STATE enum
5466 typedef enum DCCG_FIFO_ERRDET_STATE {
5472  * DCCG_FIFO_ERRDET_OVR_EN enum
5475 typedef enum DCCG_FIFO_ERRDET_OVR_EN {
5481  * DISPCLK_CHG_FWD_CORR_DISABLE enum
5484 typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
5490  * DC_MEM_GLOBAL_PWR_REQ_DIS enum
5493 typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
5499  * DCCG_PERF_RUN enum
5502 typedef enum DCCG_PERF_RUN {
5508  * DCCG_PERF_MODE_VSYNC enum
5511 typedef enum DCCG_PERF_MODE_VSYNC {
5517  * DCCG_PERF_MODE_HSYNC enum
5520 typedef enum DCCG_PERF_MODE_HSYNC {
5526  * DCCG_PERF_OTG_SELECT enum
5529 typedef enum DCCG_PERF_OTG_SELECT {
5540  * CLOCK_BRANCH_SOFT_RESET enum
5543 typedef enum CLOCK_BRANCH_SOFT_RESET {
5549  * PLL_CFG_IF_SOFT_RESET enum
5552 typedef enum PLL_CFG_IF_SOFT_RESET {
5558  * DVO_ENABLE_RST enum
5561 typedef enum DVO_ENABLE_RST {
5567  * DS_JITTER_COUNT_SRC_SEL enum
5570 typedef enum DS_JITTER_COUNT_SRC_SEL {
5576  * DIO_FIFO_ERROR enum
5579 typedef enum DIO_FIFO_ERROR {
5587  * VSYNC_CNT_REFCLK_SEL enum
5590 typedef enum VSYNC_CNT_REFCLK_SEL {
5596  * VSYNC_CNT_RESET_SEL enum
5599 typedef enum VSYNC_CNT_RESET_SEL {
5605  * VSYNC_CNT_LATCH_MASK enum
5608 typedef enum VSYNC_CNT_LATCH_MASK {
5618  * HPD_INT_CONTROL_ACK enum
5621 typedef enum HPD_INT_CONTROL_ACK {
5627  * HPD_INT_CONTROL_POLARITY enum
5630 typedef enum HPD_INT_CONTROL_POLARITY {
5636  * HPD_INT_CONTROL_RX_INT_ACK enum
5639 typedef enum HPD_INT_CONTROL_RX_INT_ACK {
5649  * DP_MSO_NUM_OF_SST_LINKS enum
5652 typedef enum DP_MSO_NUM_OF_SST_LINKS {
5659  * DP_SYNC_POLARITY enum
5662 typedef enum DP_SYNC_POLARITY {
5668  * DP_COMBINE_PIXEL_NUM enum
5671 typedef enum DP_COMBINE_PIXEL_NUM {
5678  * DP_LINK_TRAINING_COMPLETE enum
5681 typedef enum DP_LINK_TRAINING_COMPLETE {
5687  * DP_EMBEDDED_PANEL_MODE enum
5690 typedef enum DP_EMBEDDED_PANEL_MODE {
5696  * DP_PIXEL_ENCODING enum
5699 typedef enum DP_PIXEL_ENCODING {
5710  * DP_COMPONENT_DEPTH enum
5713 typedef enum DP_COMPONENT_DEPTH {
5723  * DP_UDI_LANES enum
5726 typedef enum DP_UDI_LANES {
5734  * DP_VID_STREAM_DIS_DEFER enum
5737 typedef enum DP_VID_STREAM_DIS_DEFER {
5744  * DP_STEER_OVERFLOW_ACK enum
5747 typedef enum DP_STEER_OVERFLOW_ACK {
5753  * DP_STEER_OVERFLOW_MASK enum
5756 typedef enum DP_STEER_OVERFLOW_MASK {
5762  * DP_TU_OVERFLOW_ACK enum
5765 typedef enum DP_TU_OVERFLOW_ACK {
5771  * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
5774 typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
5780  * DP_VID_M_N_GEN_EN enum
5783 typedef enum DP_VID_M_N_GEN_EN {
5789  * DP_VID_N_MUL enum
5792 typedef enum DP_VID_N_MUL {
5800  * DP_VID_ENHANCED_FRAME_MODE enum
5803 typedef enum DP_VID_ENHANCED_FRAME_MODE {
5809  * DP_VID_VBID_FIELD_POL enum
5812 typedef enum DP_VID_VBID_FIELD_POL {
5818  * DP_VID_STREAM_DISABLE_ACK enum
5821 typedef enum DP_VID_STREAM_DISABLE_ACK {
5827  * DP_VID_STREAM_DISABLE_MASK enum
5830 typedef enum DP_VID_STREAM_DISABLE_MASK {
5836  * DPHY_ATEST_SEL_LANE0 enum
5839 typedef enum DPHY_ATEST_SEL_LANE0 {
5845  * DPHY_ATEST_SEL_LANE1 enum
5848 typedef enum DPHY_ATEST_SEL_LANE1 {
5854  * DPHY_ATEST_SEL_LANE2 enum
5857 typedef enum DPHY_ATEST_SEL_LANE2 {
5863  * DPHY_ATEST_SEL_LANE3 enum
5866 typedef enum DPHY_ATEST_SEL_LANE3 {
5872  * DPHY_BYPASS enum
5875 typedef enum DPHY_BYPASS {
5881  * DPHY_SKEW_BYPASS enum
5884 typedef enum DPHY_SKEW_BYPASS {
5890  * DPHY_TRAINING_PATTERN_SEL enum
5893 typedef enum DPHY_TRAINING_PATTERN_SEL {
5901  * DPHY_8B10B_RESET enum
5904 typedef enum DPHY_8B10B_RESET {
5910  * DP_DPHY_8B10B_EXT_DISP enum
5913 typedef enum DP_DPHY_8B10B_EXT_DISP {
5919  * DPHY_8B10B_CUR_DISP enum
5922 typedef enum DPHY_8B10B_CUR_DISP {
5928  * DPHY_PRBS_EN enum
5931 typedef enum DPHY_PRBS_EN {
5937  * DPHY_PRBS_SEL enum
5940 typedef enum DPHY_PRBS_SEL {
5947  * DPHY_FEC_ENABLE enum
5950 typedef enum DPHY_FEC_ENABLE {
5956  * FEC_ACTIVE_STATUS enum
5959 typedef enum FEC_ACTIVE_STATUS {
5965  * DPHY_FEC_READY enum
5968 typedef enum DPHY_FEC_READY {
5974  * DPHY_LOAD_BS_COUNT_START enum
5977 typedef enum DPHY_LOAD_BS_COUNT_START {
5983  * DPHY_CRC_EN enum
5986 typedef enum DPHY_CRC_EN {
5992  * DPHY_CRC_CONT_EN enum
5995 typedef enum DPHY_CRC_CONT_EN {
6001  * DPHY_CRC_FIELD enum
6004 typedef enum DPHY_CRC_FIELD {
6010  * DPHY_CRC_SEL enum
6013 typedef enum DPHY_CRC_SEL {
6021  * DPHY_RX_FAST_TRAINING_CAPABLE enum
6024 typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
6030  * DP_SEC_COLLISION_ACK enum
6033 typedef enum DP_SEC_COLLISION_ACK {
6039  * DP_SEC_AUDIO_MUTE enum
6042 typedef enum DP_SEC_AUDIO_MUTE {
6048  * DP_SEC_TIMESTAMP_MODE enum
6051 typedef enum DP_SEC_TIMESTAMP_MODE {
6057  * DP_SEC_ASP_PRIORITY enum
6060 typedef enum DP_SEC_ASP_PRIORITY {
6066  * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
6069 typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
6075  * DP_MSE_SAT_UPDATE_ACT enum
6078 typedef enum DP_MSE_SAT_UPDATE_ACT {
6085  * DP_MSE_LINK_LINE enum
6088 typedef enum DP_MSE_LINK_LINE {
6096  * DP_MSE_BLANK_CODE enum
6099 typedef enum DP_MSE_BLANK_CODE {
6105  * DP_MSE_TIMESTAMP_MODE enum
6108 typedef enum DP_MSE_TIMESTAMP_MODE {
6114  * DP_MSE_ZERO_ENCODER enum
6117 typedef enum DP_MSE_ZERO_ENCODER {
6123  * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
6126 typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
6135  * DPHY_CRC_MST_PHASE_ERROR_ACK enum
6138 typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
6144  * DPHY_SW_FAST_TRAINING_START enum
6147 typedef enum DPHY_SW_FAST_TRAINING_START {
6153  * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
6156 typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
6162  * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
6165 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
6171  * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
6174 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
6180  * DP_MSA_V_TIMING_OVERRIDE_EN enum
6183 typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
6189  * DP_SEC_GSP0_PRIORITY enum
6192 typedef enum DP_SEC_GSP0_PRIORITY {
6198  * DP_SEC_GSP_SEND enum
6201 typedef enum DP_SEC_GSP_SEND {
6207  * DP_SEC_GSP_SEND_ANY_LINE enum
6210 typedef enum DP_SEC_GSP_SEND_ANY_LINE {
6216  * DP_SEC_LINE_REFERENCE enum
6219 typedef enum DP_SEC_LINE_REFERENCE {
6225  * DP_SEC_GSP_SEND_PPS enum
6228 typedef enum DP_SEC_GSP_SEND_PPS {
6234  * DP_ML_PHY_SEQ_MODE enum
6237 typedef enum DP_ML_PHY_SEQ_MODE {
6243  * DP_LINK_TRAINING_SWITCH_MODE enum
6246 typedef enum DP_LINK_TRAINING_SWITCH_MODE {
6252  * DP_DSC_MODE enum
6255 typedef enum DP_DSC_MODE {
6266  * HDMI_KEEPOUT_MODE enum
6269 typedef enum HDMI_KEEPOUT_MODE {
6275  * HDMI_CLOCK_CHANNEL_RATE enum
6278 typedef enum HDMI_CLOCK_CHANNEL_RATE {
6284  * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
6287 typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
6293  * HDMI_PACKET_GEN_VERSION enum
6296 typedef enum HDMI_PACKET_GEN_VERSION {
6302  * HDMI_ERROR_ACK enum
6305 typedef enum HDMI_ERROR_ACK {
6311  * HDMI_ERROR_MASK enum
6314 typedef enum HDMI_ERROR_MASK {
6320  * HDMI_DEEP_COLOR_DEPTH enum
6323 typedef enum HDMI_DEEP_COLOR_DEPTH {
6331  * HDMI_AUDIO_DELAY_EN enum
6334 typedef enum HDMI_AUDIO_DELAY_EN {
6342  * HDMI_AUDIO_SEND_MAX_PACKETS enum
6345 typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
6351  * HDMI_ACR_SEND enum
6354 typedef enum HDMI_ACR_SEND {
6360  * HDMI_ACR_CONT enum
6363 typedef enum HDMI_ACR_CONT {
6369  * HDMI_ACR_SELECT enum
6372 typedef enum HDMI_ACR_SELECT {
6380  * HDMI_ACR_SOURCE enum
6383 typedef enum HDMI_ACR_SOURCE {
6389  * HDMI_ACR_N_MULTIPLE enum
6392 typedef enum HDMI_ACR_N_MULTIPLE {
6404  * HDMI_ACR_AUDIO_PRIORITY enum
6407 typedef enum HDMI_ACR_AUDIO_PRIORITY {
6413  * HDMI_NULL_SEND enum
6416 typedef enum HDMI_NULL_SEND {
6422  * HDMI_GC_SEND enum
6425 typedef enum HDMI_GC_SEND {
6431  * HDMI_GC_CONT enum
6434 typedef enum HDMI_GC_CONT {
6440  * HDMI_ISRC_SEND enum
6443 typedef enum HDMI_ISRC_SEND {
6449  * HDMI_ISRC_CONT enum
6452 typedef enum HDMI_ISRC_CONT {
6458  * HDMI_AUDIO_INFO_SEND enum
6461 typedef enum HDMI_AUDIO_INFO_SEND {
6467  * HDMI_AUDIO_INFO_CONT enum
6470 typedef enum HDMI_AUDIO_INFO_CONT {
6476  * HDMI_MPEG_INFO_SEND enum
6479 typedef enum HDMI_MPEG_INFO_SEND {
6485  * HDMI_MPEG_INFO_CONT enum
6488 typedef enum HDMI_MPEG_INFO_CONT {
6494  * HDMI_GENERIC_SEND enum
6497 typedef enum HDMI_GENERIC_SEND {
6503  * HDMI_GENERIC_CONT enum
6506 typedef enum HDMI_GENERIC_CONT {
6512  * HDMI_GC_AVMUTE_CONT enum
6515 typedef enum HDMI_GC_AVMUTE_CONT {
6521  * HDMI_PACKING_PHASE_OVERRIDE enum
6524 typedef enum HDMI_PACKING_PHASE_OVERRIDE {
6530  * TMDS_PIXEL_ENCODING enum
6533 typedef enum TMDS_PIXEL_ENCODING {
6539  * TMDS_COLOR_FORMAT enum
6542 typedef enum TMDS_COLOR_FORMAT {
6550  * TMDS_STEREOSYNC_CTL_SEL_REG enum
6553 typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
6561  * TMDS_CTL0_DATA_SEL enum
6564 typedef enum TMDS_CTL0_DATA_SEL {
6576  * TMDS_CTL0_DATA_INVERT enum
6579 typedef enum TMDS_CTL0_DATA_INVERT {
6585  * TMDS_CTL0_DATA_MODULATION enum
6588 typedef enum TMDS_CTL0_DATA_MODULATION {
6596  * TMDS_CTL0_PATTERN_OUT_EN enum
6599 typedef enum TMDS_CTL0_PATTERN_OUT_EN {
6605  * TMDS_CTL1_DATA_SEL enum
6608 typedef enum TMDS_CTL1_DATA_SEL {
6620  * TMDS_CTL1_DATA_INVERT enum
6623 typedef enum TMDS_CTL1_DATA_INVERT {
6629  * TMDS_CTL1_DATA_MODULATION enum
6632 typedef enum TMDS_CTL1_DATA_MODULATION {
6640  * TMDS_CTL1_PATTERN_OUT_EN enum
6643 typedef enum TMDS_CTL1_PATTERN_OUT_EN {
6649  * TMDS_CTL2_DATA_SEL enum
6652 typedef enum TMDS_CTL2_DATA_SEL {
6664  * TMDS_CTL2_DATA_INVERT enum
6667 typedef enum TMDS_CTL2_DATA_INVERT {
6673  * TMDS_CTL2_DATA_MODULATION enum
6676 typedef enum TMDS_CTL2_DATA_MODULATION {
6684  * TMDS_CTL2_PATTERN_OUT_EN enum
6687 typedef enum TMDS_CTL2_PATTERN_OUT_EN {
6693  * TMDS_CTL3_DATA_INVERT enum
6696 typedef enum TMDS_CTL3_DATA_INVERT {
6702  * TMDS_CTL3_DATA_MODULATION enum
6705 typedef enum TMDS_CTL3_DATA_MODULATION {
6713  * TMDS_CTL3_PATTERN_OUT_EN enum
6716 typedef enum TMDS_CTL3_PATTERN_OUT_EN {
6722  * TMDS_CTL3_DATA_SEL enum
6725 typedef enum TMDS_CTL3_DATA_SEL {
6737  * DIG_FE_CNTL_SOURCE_SELECT enum
6740 typedef enum DIG_FE_CNTL_SOURCE_SELECT {
6751  * DIG_FE_CNTL_STEREOSYNC_SELECT enum
6754 typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
6765  * DIG_FIFO_READ_CLOCK_SRC enum
6768 typedef enum DIG_FIFO_READ_CLOCK_SRC {
6774  * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
6777 typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
6783  * DIG_OUTPUT_CRC_DATA_SEL enum
6786 typedef enum DIG_OUTPUT_CRC_DATA_SEL {
6794  * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
6797 typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
6803  * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
6806 typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
6812  * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
6815 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
6821  * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
6824 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
6830  * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
6833 typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
6839  * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
6842 typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
6848  * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
6851 typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
6857  * DIG_FIFO_ERROR_ACK enum
6860 typedef enum DIG_FIFO_ERROR_ACK {
6866  * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
6869 typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
6875  * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
6878 typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
6884  * AFMT_INTERRUPT_STATUS_CHG_MASK enum
6887 typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
6893  * HDMI_GC_AVMUTE enum
6896 typedef enum HDMI_GC_AVMUTE {
6902  * HDMI_DEFAULT_PAHSE enum
6905 typedef enum HDMI_DEFAULT_PAHSE {
6911  * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
6914 typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
6920  * AUDIO_LAYOUT_SELECT enum
6923 typedef enum AUDIO_LAYOUT_SELECT {
6929  * AFMT_AUDIO_CRC_CONTROL_CONT enum
6932 typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
6938  * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
6941 typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
6947  * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
6950 typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
6970  * AFMT_RAMP_CONTROL0_SIGN enum
6973 typedef enum AFMT_RAMP_CONTROL0_SIGN {
6979  * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
6982 typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
6988  * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
6991 typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
6997  * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
7000 typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
7006  * AFMT_AUDIO_SRC_CONTROL_SELECT enum
7009 typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
7020  * DIG_BE_CNTL_MODE enum
7023 typedef enum DIG_BE_CNTL_MODE {
7035  * DIG_BE_CNTL_HPD_SELECT enum
7038 typedef enum DIG_BE_CNTL_HPD_SELECT {
7049  * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
7052 typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
7058  * TMDS_SYNC_PHASE enum
7061 typedef enum TMDS_SYNC_PHASE {
7067  * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
7070 typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
7076  * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
7079 typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
7085  * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
7088 typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
7094  * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
7097 typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
7103  * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
7106 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
7114  * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
7117 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
7123  * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
7126 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
7132  * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
7135 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
7141  * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
7144 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
7150  * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
7153 typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
7159  * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
7162 typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
7168  * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
7171 typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
7177  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
7180 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
7186  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
7189 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
7195  * TMDS_REG_TEST_OUTPUTA_CNTLA enum
7198 typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
7206  * TMDS_REG_TEST_OUTPUTB_CNTLB enum
7209 typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
7217  * AFMT_VBI_GSP_INDEX enum
7220 typedef enum AFMT_VBI_GSP_INDEX {
7235  * DIG_DIGITAL_BYPASS_SEL enum
7238 typedef enum DIG_DIGITAL_BYPASS_SEL {
7249  * DIG_INPUT_PIXEL_SEL enum
7252 typedef enum DIG_INPUT_PIXEL_SEL {
7259  * DOLBY_VISION_ENABLE enum
7262 typedef enum DOLBY_VISION_ENABLE {
7268  * METADATA_HUBP_SEL enum
7271 typedef enum METADATA_HUBP_SEL {
7282  * METADATA_STREAM_TYPE_SEL enum
7285 typedef enum METADATA_STREAM_TYPE_SEL {
7291  * HDMI_METADATA_ENABLE enum
7294 typedef enum HDMI_METADATA_ENABLE {
7300  * HDMI_PACKET_LINE_REFERENCE enum
7303 typedef enum HDMI_PACKET_LINE_REFERENCE {
7313  * DP_AUX_CONTROL_HPD_SEL enum
7316 typedef enum DP_AUX_CONTROL_HPD_SEL {
7327  * DP_AUX_CONTROL_TEST_MODE enum
7330 typedef enum DP_AUX_CONTROL_TEST_MODE {
7336  * DP_AUX_SW_CONTROL_SW_GO enum
7339 typedef enum DP_AUX_SW_CONTROL_SW_GO {
7345  * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
7348 typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
7354  * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
7357 typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
7365  * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
7368 typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
7374  * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
7377 typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
7383  * DP_AUX_INT_ACK enum
7386 typedef enum DP_AUX_INT_ACK {
7392  * DP_AUX_LS_UPDATE_ACK enum
7395 typedef enum DP_AUX_LS_UPDATE_ACK {
7401  * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
7404 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
7410  * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
7413 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
7421  * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
7424 typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
7434  * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
7437 typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
7449  * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
7452 typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
7464  * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
7467 typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
7475  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
7478 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
7484  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
7487 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
7493  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
7496 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
7502  * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
7505 typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
7513  * DP_AUX_RX_TIMEOUT_LEN_MUL enum
7516 typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL {
7524  * DP_AUX_TX_PRECHARGE_LEN_MUL enum
7527 typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL {
7535  * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
7538 typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
7550  * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
7553 typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
7559  * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
7562 typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
7570  * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
7573 typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
7581  * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
7584 typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
7592  * DP_AUX_ERR_OCCURRED_ACK enum
7595 typedef enum DP_AUX_ERR_OCCURRED_ACK {
7601  * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
7604 typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
7610  * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
7613 typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
7619  * DP_AUX_RESET enum
7622 typedef enum DP_AUX_RESET {
7628  * DP_AUX_RESET_DONE enum
7631 typedef enum DP_AUX_RESET_DONE {
7637  * DP_AUX_PHY_WAKE_PRIORITY enum
7640 typedef enum DP_AUX_PHY_WAKE_PRIORITY {
7650  * DOUT_I2C_CONTROL_GO enum
7653 typedef enum DOUT_I2C_CONTROL_GO {
7659  * DOUT_I2C_CONTROL_SOFT_RESET enum
7662 typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
7668  * DOUT_I2C_CONTROL_SEND_RESET enum
7671 typedef enum DOUT_I2C_CONTROL_SEND_RESET {
7677  * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum
7680 typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH {
7686  * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
7689 typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
7695  * DOUT_I2C_CONTROL_DDC_SELECT enum
7698 typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
7709  * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
7712 typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
7720  * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
7723 typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
7731  * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
7734 typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
7740  * DOUT_I2C_ARBITRATION_ABORT_XFER enum
7743 typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
7749  * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
7752 typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
7758  * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
7761 typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
7767  * DOUT_I2C_ACK enum
7770 typedef enum DOUT_I2C_ACK {
7776  * DOUT_I2C_DDC_SPEED_THRESHOLD enum
7779 typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
7787  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
7790 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
7796  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
7799 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
7805  * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
7808 typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
7814  * DOUT_I2C_DDC_EDID_DETECT_STATUS enum
7817 typedef enum DOUT_I2C_DDC_EDID_DETECT_STATUS {
7823  * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
7826 typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
7832  * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
7835 typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
7841  * DOUT_I2C_DATA_INDEX_WRITE enum
7844 typedef enum DOUT_I2C_DATA_INDEX_WRITE {
7850  * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
7853 typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
7859  * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
7862 typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
7872  * DIOMEM_PWR_FORCE_CTRL enum
7875 typedef enum DIOMEM_PWR_FORCE_CTRL {
7883  * DIOMEM_PWR_FORCE_CTRL2 enum
7886 typedef enum DIOMEM_PWR_FORCE_CTRL2 {
7892  * DIOMEM_PWR_DIS_CTRL enum
7895 typedef enum DIOMEM_PWR_DIS_CTRL {
7901  * CLOCK_GATING_EN enum
7904 typedef enum CLOCK_GATING_EN {
7910  * DIOMEM_PWR_SEL_CTRL enum
7913 typedef enum DIOMEM_PWR_SEL_CTRL {
7920  * DIOMEM_PWR_SEL_CTRL2 enum
7923 typedef enum DIOMEM_PWR_SEL_CTRL2 {
7929  * PM_ASSERT_RESET enum
7932 typedef enum PM_ASSERT_RESET {
7938  * DAC_MUX_SELECT enum
7941 typedef enum DAC_MUX_SELECT {
7947  * TMDS_MUX_SELECT enum
7950 typedef enum TMDS_MUX_SELECT {
7958  * SOFT_RESET enum
7961 typedef enum SOFT_RESET {
7967  * GENERIC_STEREOSYNC_SEL enum
7970 typedef enum GENERIC_STEREOSYNC_SEL {
7981  * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum
7984 typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE {
7990  * DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE enum
7993 typedef enum DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE {
8003  * DCIO_DC_GENERICA_SEL enum
8006 typedef enum DCIO_DC_GENERICA_SEL {
8028  * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
8031 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
8042  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
8045 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
8056  * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
8059 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
8070  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
8073 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
8084  * DCIO_DC_GENERICB_SEL enum
8087 typedef enum DCIO_DC_GENERICB_SEL {
8107  * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
8110 typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
8118  * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
8121 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
8129  * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum
8132 typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
8144  * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
8147 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
8153  * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
8156 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
8164  * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
8167 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
8175  * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum
8178 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
8184  * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum
8187 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
8193  * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum
8196 typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
8202  * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum
8205 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
8211  * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum
8214 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
8220  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum
8223 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
8229  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum
8232 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
8238  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum
8241 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
8247  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum
8250 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
8256  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum
8259 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
8265  * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum
8268 typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
8274  * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
8277 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
8283  * DCIO_BL_PWM_CNTL_BL_PWM_EN enum
8286 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
8292  * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
8295 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
8301  * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum
8304 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
8310  * DCIO_BL_PWM_GRP1_REG_LOCK enum
8313 typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
8319  * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
8322 typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
8328  * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
8331 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
8341  * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
8344 typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
8350  * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
8353 typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
8359  * DCIO_GSL_SEL enum
8362 typedef enum DCIO_GSL_SEL {
8369  * DCIO_GENLK_CLK_GSL_MASK enum
8372 typedef enum DCIO_GENLK_CLK_GSL_MASK {
8379  * DCIO_GENLK_VSYNC_GSL_MASK enum
8382 typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
8389  * DCIO_SWAPLOCK_A_GSL_MASK enum
8392 typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
8399  * DCIO_SWAPLOCK_B_GSL_MASK enum
8402 typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
8409  * DCIO_DC_GPU_TIMER_START_POSITION enum
8412 typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
8424  * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
8427 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
8434  * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
8437 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
8443  * DCIO_DIO_OTG_EXT_VSYNC_MUX enum
8446 typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX {
8458  * DCIO_DIO_EXT_VSYNC_MASK enum
8461 typedef enum DCIO_DIO_EXT_VSYNC_MASK {
8473  * DCIO_DSYNC_SOFT_RESET enum
8476 typedef enum DCIO_DSYNC_SOFT_RESET {
8482  * DCIO_DACA_SOFT_RESET enum
8485 typedef enum DCIO_DACA_SOFT_RESET {
8491  * DCIO_DCRXPHY_SOFT_RESET enum
8494 typedef enum DCIO_DCRXPHY_SOFT_RESET {
8500  * DCIO_DPHY_LANE_SEL enum
8503 typedef enum DCIO_DPHY_LANE_SEL {
8511  * DCIO_DPCS_INTERRUPT_TYPE enum
8514 typedef enum DCIO_DPCS_INTERRUPT_TYPE {
8520  * DCIO_DPCS_INTERRUPT_MASK enum
8523 typedef enum DCIO_DPCS_INTERRUPT_MASK {
8529  * DCIO_DC_GPU_TIMER_READ_SELECT enum
8532 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
8542  * DCIO_IMPCAL_STEP_DELAY enum
8545 typedef enum DCIO_IMPCAL_STEP_DELAY {
8565  * DCIO_UNIPHY_IMPCAL_SEL enum
8568 typedef enum DCIO_UNIPHY_IMPCAL_SEL {
8578  * DCIOCHIP_HPD_SEL enum
8581 typedef enum DCIOCHIP_HPD_SEL {
8587  * DCIOCHIP_PAD_MODE enum
8590 typedef enum DCIOCHIP_PAD_MODE {
8596  * DCIOCHIP_AUXSLAVE_PAD_MODE enum
8599 typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
8605  * DCIOCHIP_INVERT enum
8608 typedef enum DCIOCHIP_INVERT {
8614  * DCIOCHIP_PD_EN enum
8617 typedef enum DCIOCHIP_PD_EN {
8623  * DCIOCHIP_GPIO_MASK_EN enum
8626 typedef enum DCIOCHIP_GPIO_MASK_EN {
8632  * DCIOCHIP_MASK enum
8635 typedef enum DCIOCHIP_MASK {
8641  * DCIOCHIP_GPIO_I2C_MASK enum
8644 typedef enum DCIOCHIP_GPIO_I2C_MASK {
8650  * DCIOCHIP_GPIO_I2C_DRIVE enum
8653 typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
8659  * DCIOCHIP_GPIO_I2C_EN enum
8662 typedef enum DCIOCHIP_GPIO_I2C_EN {
8668  * DCIOCHIP_MASK_4BIT enum
8671 typedef enum DCIOCHIP_MASK_4BIT {
8677  * DCIOCHIP_ENABLE_4BIT enum
8680 typedef enum DCIOCHIP_ENABLE_4BIT {
8686  * DCIOCHIP_MASK_5BIT enum
8689 typedef enum DCIOCHIP_MASK_5BIT {
8695  * DCIOCHIP_ENABLE_5BIT enum
8698 typedef enum DCIOCHIP_ENABLE_5BIT {
8704  * DCIOCHIP_MASK_2BIT enum
8707 typedef enum DCIOCHIP_MASK_2BIT {
8713  * DCIOCHIP_ENABLE_2BIT enum
8716 typedef enum DCIOCHIP_ENABLE_2BIT {
8722  * DCIOCHIP_REF_27_SRC_SEL enum
8725 typedef enum DCIOCHIP_REF_27_SRC_SEL {
8733  * DCIOCHIP_DVO_VREFPON enum
8736 typedef enum DCIOCHIP_DVO_VREFPON {
8742  * DCIOCHIP_DVO_VREFSEL enum
8745 typedef enum DCIOCHIP_DVO_VREFSEL {
8751  * DCIOCHIP_SPDIF1_IMODE enum
8754 typedef enum DCIOCHIP_SPDIF1_IMODE {
8760  * DCIOCHIP_AUX_FALLSLEWSEL enum
8763 typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
8771  * DCIOCHIP_I2C_FALLSLEWSEL enum
8774 typedef enum DCIOCHIP_I2C_FALLSLEWSEL {
8782  * DCIOCHIP_AUX_SPIKESEL enum
8785 typedef enum DCIOCHIP_AUX_SPIKESEL {
8791  * DCIOCHIP_AUX_CSEL0P9 enum
8794 typedef enum DCIOCHIP_AUX_CSEL0P9 {
8800  * DCIOCHIP_AUX_CSEL1P1 enum
8803 typedef enum DCIOCHIP_AUX_CSEL1P1 {
8809  * DCIOCHIP_AUX_RSEL0P9 enum
8812 typedef enum DCIOCHIP_AUX_RSEL0P9 {
8818  * DCIOCHIP_AUX_RSEL1P1 enum
8821 typedef enum DCIOCHIP_AUX_RSEL1P1 {
8827  * DCIOCHIP_AUX_HYS_TUNE enum
8830 typedef enum DCIOCHIP_AUX_HYS_TUNE {
8838  * DCIOCHIP_AUX_VOD_TUNE enum
8841 typedef enum DCIOCHIP_AUX_VOD_TUNE {
8849  * DCIOCHIP_I2C_VPH_1V2_EN enum
8852 typedef enum DCIOCHIP_I2C_VPH_1V2_EN {
8858  * DCIOCHIP_I2C_COMPSEL enum
8861 typedef enum DCIOCHIP_I2C_COMPSEL {
8867  * DCIOCHIP_AUX_ALL_PWR_OK enum
8870 typedef enum DCIOCHIP_AUX_ALL_PWR_OK {
8876  * DCIOCHIP_I2C_RECEIVER_SEL enum
8879 typedef enum DCIOCHIP_I2C_RECEIVER_SEL {
8887  * DCIOCHIP_AUX_RECEIVER_SEL enum
8890 typedef enum DCIOCHIP_AUX_RECEIVER_SEL {
8902  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
8905 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
8911  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
8914 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
8920  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
8923 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
8929  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
8932 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
8938  * AZ_GLOBAL_CAPABILITIES enum
8941 typedef enum AZ_GLOBAL_CAPABILITIES {
8947  * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
8950 typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
8956  * GLOBAL_CONTROL_FLUSH_CONTROL enum
8959 typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
8965  * GLOBAL_CONTROL_CONTROLLER_RESET enum
8968 typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
8974  * AZ_STATE_CHANGE_STATUS enum
8977 typedef enum AZ_STATE_CHANGE_STATUS {
8983  * GLOBAL_STATUS_FLUSH_STATUS enum
8986 typedef enum GLOBAL_STATUS_FLUSH_STATUS {
8992  * STREAM_0_SYNCHRONIZATION enum
8995 typedef enum STREAM_0_SYNCHRONIZATION {
9001  * STREAM_1_SYNCHRONIZATION enum
9004 typedef enum STREAM_1_SYNCHRONIZATION {
9010  * STREAM_2_SYNCHRONIZATION enum
9013 typedef enum STREAM_2_SYNCHRONIZATION {
9019  * STREAM_3_SYNCHRONIZATION enum
9022 typedef enum STREAM_3_SYNCHRONIZATION {
9028  * STREAM_4_SYNCHRONIZATION enum
9031 typedef enum STREAM_4_SYNCHRONIZATION {
9037  * STREAM_5_SYNCHRONIZATION enum
9040 typedef enum STREAM_5_SYNCHRONIZATION {
9046  * STREAM_6_SYNCHRONIZATION enum
9049 typedef enum STREAM_6_SYNCHRONIZATION {
9055  * STREAM_7_SYNCHRONIZATION enum
9058 typedef enum STREAM_7_SYNCHRONIZATION {
9064  * STREAM_8_SYNCHRONIZATION enum
9067 typedef enum STREAM_8_SYNCHRONIZATION {
9073  * STREAM_9_SYNCHRONIZATION enum
9076 typedef enum STREAM_9_SYNCHRONIZATION {
9082  * STREAM_10_SYNCHRONIZATION enum
9085 typedef enum STREAM_10_SYNCHRONIZATION {
9091  * STREAM_11_SYNCHRONIZATION enum
9094 typedef enum STREAM_11_SYNCHRONIZATION {
9100  * STREAM_12_SYNCHRONIZATION enum
9103 typedef enum STREAM_12_SYNCHRONIZATION {
9109  * STREAM_13_SYNCHRONIZATION enum
9112 typedef enum STREAM_13_SYNCHRONIZATION {
9118  * STREAM_14_SYNCHRONIZATION enum
9121 typedef enum STREAM_14_SYNCHRONIZATION {
9127  * STREAM_15_SYNCHRONIZATION enum
9130 typedef enum STREAM_15_SYNCHRONIZATION {
9136  * CORB_READ_POINTER_RESET enum
9139 typedef enum CORB_READ_POINTER_RESET {
9145  * AZ_CORB_SIZE enum
9148 typedef enum AZ_CORB_SIZE {
9156  * AZ_RIRB_WRITE_POINTER_RESET enum
9159 typedef enum AZ_RIRB_WRITE_POINTER_RESET {
9165  * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
9168 typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
9174  * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
9177 typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
9183  * AZ_RIRB_SIZE enum
9186 typedef enum AZ_RIRB_SIZE {
9194  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
9197 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
9203  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
9206 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
9212  * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
9215 typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
9225  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
9228 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
9234  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
9237 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
9243  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
9246 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
9255  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
9258 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
9270  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
9273 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
9283  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
9286 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
9299  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
9302 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
9308  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
9311 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
9317  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
9320 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
9326  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
9329 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
9335  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
9338 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
9344  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
9347 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
9353  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
9356 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
9362  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
9365 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
9371  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
9374 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
9380  * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
9383 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
9389  * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
9392 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
9398  * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
9401 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
9407  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
9410 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
9416  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
9419 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
9425  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
9428 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
9434  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
9437 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
9443  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
9446 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
9452  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
9455 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
9461  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
9464 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
9470  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
9473 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
9479  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
9482 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
9488  * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum
9491 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE {
9515  * MEM_PWR_FORCE_CTRL enum
9518 typedef enum MEM_PWR_FORCE_CTRL {
9526  * MEM_PWR_FORCE_CTRL2 enum
9529 typedef enum MEM_PWR_FORCE_CTRL2 {
9535  * MEM_PWR_DIS_CTRL enum
9538 typedef enum MEM_PWR_DIS_CTRL {
9544  * MEM_PWR_SEL_CTRL enum
9547 typedef enum MEM_PWR_SEL_CTRL {
9554  * MEM_PWR_SEL_CTRL2 enum
9557 typedef enum MEM_PWR_SEL_CTRL2 {
9563  * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
9566 typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
9576  * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
9579 typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
9591  * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
9594 typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
9610  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
9613 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
9619  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
9622 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
9628  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
9631 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
9640  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
9643 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
9655  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
9658 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
9668  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
9671 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
9684  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
9687 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
9693  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
9696 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
9702  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
9705 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
9711  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
9714 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
9720  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
9723 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
9729  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
9732 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
9738  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
9741 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
9747  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
9750 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
9756  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
9759 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
9765  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
9768 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
9774  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
9777 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
9787  * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
9790 typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
9800  * AZ_LATENCY_COUNTER_CONTROL enum
9803 typedef enum AZ_LATENCY_COUNTER_CONTROL {
9813  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
9816 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
9822  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
9825 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
9831  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
9834 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
9840  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
9843 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
9849  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
9852 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
9858  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
9861 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
9867  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
9870 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
9876  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
9879 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
9885  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
9888 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
9894  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
9897 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
9903  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
9906 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
9915  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
9918 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
9930  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
9933 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
9943  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
9946 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
9970  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
9973 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
9987  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
9990 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
9996  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
9999 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10005  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10008 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10014  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10017 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10023 … AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10026 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAP…
10032  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10035 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10041  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10044 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10050  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
10053 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
10059  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10062 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVER…
10068  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10071 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT…
10077  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10080 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10086  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
10089 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITI…
10095  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
10098 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
10112  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
10115 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
10121  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
10124 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10130  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10133 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10139  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10142 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10148  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10151 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILIT…
10157  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10160 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10166  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10169 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10175  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10178 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10184  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10187 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
10193  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10196 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10202  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
10205 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
10211  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
10214 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
10220  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
10223 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
10229  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
10232 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
10238  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
10241 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
10247  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
10250 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
10256  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
10259 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
10265  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
10268 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
10274  * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10277 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10283  * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
10286 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
10296  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
10299 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
10313  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
10316 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
10322  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
10325 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10331  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10334 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10340  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10343 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10349 …A_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10352 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPON…
10358  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10361 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10367  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10370 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10376  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
10379 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
10385 …ALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10388 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETE…
10394  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10397 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_P…
10403  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10406 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PR…
10412 …AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
10415 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPA…
10421  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
10424 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
10438  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
10441 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
10447  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
10450 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10456  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10459 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10465  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10468 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10474 … AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10477 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAP…
10483  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10486 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10492  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10495 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10501  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10504 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVER…
10510  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10513 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT…
10519  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10522 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10528  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
10531 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
10537  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
10540 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
10546  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
10549 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
10555  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
10558 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
10564  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
10567 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
10573  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
10576 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
10582  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
10585 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
10591  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
10594 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
10600  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
10603 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
10609  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
10612 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
10618  * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
10621 typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
10631  * DSCC_ICH_RESET_ENUM enum
10634 typedef enum DSCC_ICH_RESET_ENUM {
10642  * DSCC_DSC_VERSION_MINOR_ENUM enum
10645 typedef enum DSCC_DSC_VERSION_MINOR_ENUM {
10651  * DSCC_DSC_VERSION_MAJOR_ENUM enum
10654 typedef enum DSCC_DSC_VERSION_MAJOR_ENUM {
10659  * DSCC_LINEBUF_DEPTH_ENUM enum
10662 typedef enum DSCC_LINEBUF_DEPTH_ENUM {
10672  * DSCC_BITS_PER_COMPONENT_ENUM enum
10675 typedef enum DSCC_BITS_PER_COMPONENT_ENUM {
10682  * DSCC_ENABLE_ENUM enum
10685 typedef enum DSCC_ENABLE_ENUM {
10691  * DSCC_MEM_PWR_FORCE_ENUM enum
10694 typedef enum DSCC_MEM_PWR_FORCE_ENUM {
10702  * POWER_STATE_ENUM enum
10705 typedef enum POWER_STATE_ENUM {
10713  * DSCC_MEM_PWR_DIS_ENUM enum
10716 typedef enum DSCC_MEM_PWR_DIS_ENUM {
10726  * DSCCIF_ENABLE_ENUM enum
10729 typedef enum DSCCIF_ENABLE_ENUM {
10735  * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum
10738 typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM {
10747  * DSCCIF_BITS_PER_COMPONENT_ENUM enum
10750 typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM {
10761  * ENABLE_ENUM enum
10764 typedef enum ENABLE_ENUM {
10770  * CLOCK_GATING_DISABLE_ENUM enum
10773 typedef enum CLOCK_GATING_DISABLE_ENUM {
10779  * TEST_CLOCK_MUX_SELECT_ENUM enum
10782 typedef enum TEST_CLOCK_MUX_SELECT_ENUM {
10796  * WB_ENABLE_ENUM enum
10799 typedef enum WB_ENABLE_ENUM {
10805  * WB_CLK_GATE_DIS_ENUM enum
10808 typedef enum WB_CLK_GATE_DIS_ENUM {
10814  * WB_MEM_PWR_DIS_ENUM enum
10817 typedef enum WB_MEM_PWR_DIS_ENUM {
10823  * WB_TEST_CLK_SEL_ENUM enum
10826 typedef enum WB_TEST_CLK_SEL_ENUM {
10834  * WBSCL_LB_MEM_PWR_MODE_SEL_ENUM enum
10837 typedef enum WBSCL_LB_MEM_PWR_MODE_SEL_ENUM {
10845  * WBSCL_LB_MEM_PWR_FORCE_ENUM enum
10848 typedef enum WBSCL_LB_MEM_PWR_FORCE_ENUM {
10856  * WBSCL_MEM_PWR_STATE_ENUM enum
10859 typedef enum WBSCL_MEM_PWR_STATE_ENUM {
10867  * WBSCL_LUT_MEM_PWR_STATE_ENUM enum
10870 typedef enum WBSCL_LUT_MEM_PWR_STATE_ENUM {
10878  * WB_RAM_PW_SAVE_MODE_ENUM enum
10881 typedef enum WB_RAM_PW_SAVE_MODE_ENUM {
10887  * CNV_OUT_BPC_ENUM enum
10890 typedef enum CNV_OUT_BPC_ENUM {
10896  * CNV_FRAME_CAPTURE_RATE_ENUM enum
10899 typedef enum CNV_FRAME_CAPTURE_RATE_ENUM {
10907  * CNV_WINDOW_CROP_EN_ENUM enum
10910 typedef enum CNV_WINDOW_CROP_EN_ENUM {
10916  * CNV_INTERLACED_MODE_ENUM enum
10919 typedef enum CNV_INTERLACED_MODE_ENUM {
10925  * CNV_EYE_SELECT enum
10928 typedef enum CNV_EYE_SELECT {
10936  * CNV_STEREO_TYPE_ENUM enum
10939 typedef enum CNV_STEREO_TYPE_ENUM {
10947  * CNV_STEREO_POLARITY_ENUM enum
10950 typedef enum CNV_STEREO_POLARITY_ENUM {
10956  * CNV_INTERLACED_FIELD_ORDER_ENUM enum
10959 typedef enum CNV_INTERLACED_FIELD_ORDER_ENUM {
10965  * CNV_STEREO_SPLIT_ENUM enum
10968 typedef enum CNV_STEREO_SPLIT_ENUM {
10974  * CNV_NEW_CONTENT_ENUM enum
10977 typedef enum CNV_NEW_CONTENT_ENUM {
10983  * CNV_FRAME_CAPTURE_EN_ENUM enum
10986 typedef enum CNV_FRAME_CAPTURE_EN_ENUM {
10992  * CNV_UPDATE_PENDING_ENUM enum
10995 typedef enum CNV_UPDATE_PENDING_ENUM {
11001  * CNV_UPDATE_LOCK_ENUM enum
11004 typedef enum CNV_UPDATE_LOCK_ENUM {
11010  * CNV_CSC_BYPASS_ENUM enum
11013 typedef enum CNV_CSC_BYPASS_ENUM {
11019  * CNV_TEST_CRC_EN_ENUM enum
11022 typedef enum CNV_TEST_CRC_EN_ENUM {
11028  * CNV_TEST_CRC_CONT_EN_ENUM enum
11031 typedef enum CNV_TEST_CRC_CONT_EN_ENUM {
11037  * WB_SOFT_RESET_ENUM enum
11040 typedef enum WB_SOFT_RESET_ENUM {
11046  * DWB_GMC_WARM_UP_ENABLE_ENUM enum
11049 typedef enum DWB_GMC_WARM_UP_ENABLE_ENUM {
11055  * DWB_MODE_WARMUP_ENUM enum
11058 typedef enum DWB_MODE_WARMUP_ENUM {
11064  * DWB_DATA_DEPTH_WARMUP_ENUM enum
11067 typedef enum DWB_DATA_DEPTH_WARMUP_ENUM {
11077  * WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM enum
11080 typedef enum WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM {
11090  * WBSCL_COEF_RAM_PHASE_ENUM enum
11093 typedef enum WBSCL_COEF_RAM_PHASE_ENUM {
11106  * WBSCL_COEF_RAM_FILTER_TYPE_ENUM enum
11109 typedef enum WBSCL_COEF_RAM_FILTER_TYPE_ENUM {
11117  * WBSCL_COEF_FILTER_TYPE_SEL enum
11120 typedef enum WBSCL_COEF_FILTER_TYPE_SEL {
11128  * WBSCL_MODE_SEL enum
11131 typedef enum WBSCL_MODE_SEL {
11139  * WBSCL_PIXEL_DEPTH enum
11142 typedef enum WBSCL_PIXEL_DEPTH {
11148  * WBSCL_COEF_RAM_SEL_ENUM enum
11151 typedef enum WBSCL_COEF_RAM_SEL_ENUM {
11157  * WBSCL_COEF_RAM_RD_SEL_ENUM enum
11160 typedef enum WBSCL_COEF_RAM_RD_SEL_ENUM {
11166  * WBSCL_COEF_RAM_TAP_COEF_EN_ENUM enum
11169 typedef enum WBSCL_COEF_RAM_TAP_COEF_EN_ENUM {
11175  * WBSCL_NUM_OF_TAPS_ENUM enum
11178 typedef enum WBSCL_NUM_OF_TAPS_ENUM {
11194  * WBSCL_STATUS_ACK_ENUM enum
11197 typedef enum WBSCL_STATUS_ACK_ENUM {
11203  * WBSCL_STATUS_MASK_ENUM enum
11206 typedef enum WBSCL_STATUS_MASK_ENUM {
11212  * WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM enum
11215 typedef enum WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM {
11221  * WBSCL_HOST_CONFLICT_INT_TYPE_ENUM enum
11224 typedef enum WBSCL_HOST_CONFLICT_INT_TYPE_ENUM {
11230  * WBSCL_TEST_CRC_EN_ENUM enum
11233 typedef enum WBSCL_TEST_CRC_EN_ENUM {
11239  * WBSCL_TEST_CRC_CONT_EN_ENUM enum
11242 typedef enum WBSCL_TEST_CRC_CONT_EN_ENUM {
11248  * WBSCL_TEST_CRC_MASK_ENUM enum
11251 typedef enum WBSCL_TEST_CRC_MASK_ENUM {
11257  * WBSCL_BACKPRESSURE_CNT_EN_ENUM enum
11260 typedef enum WBSCL_BACKPRESSURE_CNT_EN_ENUM {
11266  * WBSCL_OUTSIDE_PIX_STRATEGY_ENUM enum
11269 typedef enum WBSCL_OUTSIDE_PIX_STRATEGY_ENUM {
11279  * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum
11282 typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
11294  * DPCSTX_DVI_LINK_MODE enum
11297 typedef enum DPCSTX_DVI_LINK_MODE {
11308  * RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET enum
11311 typedef enum RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET {
11317  * RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET enum
11320 typedef enum RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET {
11325  * RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN enum
11328 typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN {
11334  * RDPCSTX_CNTL_RDPCS_TX_FIFO_EN enum
11337 typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_EN {
11343  * RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET enum
11346 typedef enum RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET {
11352  * RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN enum
11355 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN {
11361  * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN enum
11364 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN {
11370  * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS enum
11373 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS {
11379  * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN enum
11382 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN {
11388  * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON enum
11391 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON {
11397  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum
11400 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS {
11406  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum
11409 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN {
11415  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS enum
11418 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS {
11424  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum
11427 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON {
11433  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum
11436 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE {
11442  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum
11445 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE {
11451  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum
11454 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK {
11460  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum
11463 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK {
11469  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum
11472 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK {
11478  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK enum
11481 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK {
11487  * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum
11490 typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE {
11498  * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum
11501 typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE {
11509  * RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF enum
11512 typedef enum RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF {
11520  * RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum
11523 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE {
11535  * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum
11538 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL {
11544  * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum
11547 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL {
11553  * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum
11556 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE {
11562  * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum
11565 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE {
11571  * RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum
11574 typedef enum RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL {
11586  * RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum
11589 typedef enum RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE {
11597  * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum
11600 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE {
11607  * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum
11610 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH {
11618  * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum
11621 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT {
11627  * RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum
11630 typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV {
11639  * RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum
11642 typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV {
11650  * RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum
11653 typedef enum RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV {
11665  * RDPCS_TEST_CLK_SEL enum
11668 typedef enum RDPCS_TEST_CLK_SEL {
11694  * CBMode enum
11697 typedef enum CBMode {
11709  * BlendOp enum
11712 typedef enum BlendOp {
11737  * CombFunc enum
11740 typedef enum CombFunc {
11749  * BlendOpt enum
11752 typedef enum BlendOpt {
11764  * CmaskCode enum
11767 typedef enum CmaskCode {
11787  * MemArbMode enum
11790 typedef enum MemArbMode {
11798  * CBPerfOpFilterSel enum
11801 typedef enum CBPerfOpFilterSel {
11811  * CBPerfClearFilterSel enum
11814 typedef enum CBPerfClearFilterSel {
11820  * CBPerfSel enum
11823 typedef enum CBPerfSel {
12271  * CmaskAddr enum
12274 typedef enum CmaskAddr {
12281  * SourceFormat enum
12284 typedef enum SourceFormat {
12296  * TC_OP_MASKS enum
12299 typedef enum TC_OP_MASKS {
12306  * TC_OP enum
12309 typedef enum TC_OP {
12441  * TC_NACKS enum
12444 typedef enum TC_NACKS {
12452  * TC_EA_CID enum
12455 typedef enum TC_EA_CID {
12479  * GL2_OP_MASKS enum
12482 typedef enum GL2_OP_MASKS {
12489  * GL2_OP enum
12492 typedef enum GL2_OP {
12580  * GL2_NACKS enum
12583 typedef enum GL2_NACKS {
12591  * GL2_EA_CID enum
12594 typedef enum GL2_EA_CID {
12615  * SPI_SAMPLE_CNTL enum
12618 typedef enum SPI_SAMPLE_CNTL {
12626  * SPI_FOG_MODE enum
12629 typedef enum SPI_FOG_MODE {
12637  * SPI_PNT_SPRITE_OVERRIDE enum
12640 typedef enum SPI_PNT_SPRITE_OVERRIDE {
12649  * SPI_PERFCNT_SEL enum
12652 typedef enum SPI_PERFCNT_SEL {
12938  * SPI_SHADER_FORMAT enum
12941 typedef enum SPI_SHADER_FORMAT {
12950  * SPI_SHADER_EX_FORMAT enum
12953 typedef enum SPI_SHADER_EX_FORMAT {
12967  * CLKGATE_SM_MODE enum
12970 typedef enum CLKGATE_SM_MODE {
12979  * CLKGATE_BASE_MODE enum
12982 typedef enum CLKGATE_BASE_MODE {
12988  * SPI_LB_WAVES_SELECT enum
12991 typedef enum SPI_LB_WAVES_SELECT {
13003  * SQ_TEX_CLAMP enum
13006 typedef enum SQ_TEX_CLAMP {
13018  * SQ_TEX_XY_FILTER enum
13021 typedef enum SQ_TEX_XY_FILTER {
13029  * SQ_TEX_Z_FILTER enum
13032 typedef enum SQ_TEX_Z_FILTER {
13039  * SQ_TEX_MIP_FILTER enum
13042 typedef enum SQ_TEX_MIP_FILTER {
13050  * SQ_TEX_ANISO_RATIO enum
13053 typedef enum SQ_TEX_ANISO_RATIO {
13062  * SQ_TEX_DEPTH_COMPARE enum
13065 typedef enum SQ_TEX_DEPTH_COMPARE {
13077  * SQ_TEX_BORDER_COLOR enum
13080 typedef enum SQ_TEX_BORDER_COLOR {
13088  * SQ_RSRC_BUF_TYPE enum
13091 typedef enum SQ_RSRC_BUF_TYPE {
13099  * SQ_RSRC_IMG_TYPE enum
13102 typedef enum SQ_RSRC_IMG_TYPE {
13122  * SQ_RSRC_FLAT_TYPE enum
13125 typedef enum SQ_RSRC_FLAT_TYPE {
13133  * SQ_IMG_FILTER_TYPE enum
13136 typedef enum SQ_IMG_FILTER_TYPE {
13143  * SQ_SEL_XYZW01 enum
13146 typedef enum SQ_SEL_XYZW01 {
13158  * SQ_OOB_SELECT enum
13161 typedef enum SQ_OOB_SELECT {
13169  * SQ_WAVE_TYPE enum
13172 typedef enum SQ_WAVE_TYPE {
13186  * SQ_PERF_SEL enum
13189 typedef enum SQ_PERF_SEL {
13555  * SQ_CAC_POWER_SEL enum
13558 typedef enum SQ_CAC_POWER_SEL {
13571  * SQ_IND_CMD_CMD enum
13574 typedef enum SQ_IND_CMD_CMD {
13587  * SQ_IND_CMD_MODE enum
13590 typedef enum SQ_IND_CMD_MODE {
13599  * SQ_EDC_INFO_SOURCE enum
13602 typedef enum SQ_EDC_INFO_SOURCE {
13613  * SQ_ROUND_MODE enum
13616 typedef enum SQ_ROUND_MODE {
13624  * SQ_INTERRUPT_WORD_ENCODING enum
13627 typedef enum SQ_INTERRUPT_WORD_ENCODING {
13634  * SQ_IBUF_ST enum
13637 typedef enum SQ_IBUF_ST {
13649  * SQ_INST_STR_ST enum
13652 typedef enum SQ_INST_STR_ST {
13664  * SQ_WAVE_IB_ECC_ST enum
13667 typedef enum SQ_WAVE_IB_ECC_ST {
13675  * SH_MEM_ADDRESS_MODE enum
13678 typedef enum SH_MEM_ADDRESS_MODE {
13684  * SH_MEM_RETRY_MODE enum
13687 typedef enum SH_MEM_RETRY_MODE {
13694  * SH_MEM_ALIGNMENT_MODE enum
13697 typedef enum SH_MEM_ALIGNMENT_MODE {
13705  * SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT enum
13708 typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT {
13720  * SQ_TT_TOKEN_MASK_REG_INCLUDE enum
13723 typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE {
13735  * SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT enum
13738 typedef enum SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT {
13754  * SQ_TT_TOKEN_MASK_INST_EXCLUDE enum
13757 typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE {
13763  * SQ_TT_MODE enum
13766 typedef enum SQ_TT_MODE {
13774  * SQ_TT_WTYPE_INCLUDE_SHIFT enum
13777 typedef enum SQ_TT_WTYPE_INCLUDE_SHIFT {
13788  * SQ_TT_WTYPE_INCLUDE enum
13791 typedef enum SQ_TT_WTYPE_INCLUDE {
13802  * SQ_TT_UTIL_TIMER enum
13805 typedef enum SQ_TT_UTIL_TIMER {
13811  * SQ_TT_WAVESTART_MODE enum
13814 typedef enum SQ_TT_WAVESTART_MODE {
13821  * SQ_TT_RT_FREQ enum
13824 typedef enum SQ_TT_RT_FREQ {
13831  * SQ_WATCH_MODES enum
13834 typedef enum SQ_WATCH_MODES {
13842  * SQ_WAVE_SCHED_MODES enum
13845 typedef enum SQ_WAVE_SCHED_MODES {
14009  * CSDATA_TYPE enum
14012 typedef enum CSDATA_TYPE {
14020  * CSCNTL_TYPE enum
14023 typedef enum CSCNTL_TYPE {
14071  * VGT_OUT_PRIM_TYPE enum
14074 typedef enum VGT_OUT_PRIM_TYPE {
14093  * VGT_DI_PRIM_TYPE enum
14096 typedef enum VGT_DI_PRIM_TYPE {
14122  * VGT_DI_SOURCE_SELECT enum
14125 typedef enum VGT_DI_SOURCE_SELECT {
14133  * VGT_DI_MAJOR_MODE_SELECT enum
14136 typedef enum VGT_DI_MAJOR_MODE_SELECT {
14142  * VGT_DI_INDEX_SIZE enum
14145 typedef enum VGT_DI_INDEX_SIZE {
14152  * VGT_EVENT_TYPE enum
14155 typedef enum VGT_EVENT_TYPE {
14223  * VGT_DMA_SWAP_MODE enum
14226 typedef enum VGT_DMA_SWAP_MODE {
14234  * VGT_INDEX_TYPE_MODE enum
14237 typedef enum VGT_INDEX_TYPE_MODE {
14244  * VGT_DMA_BUF_TYPE enum
14247 typedef enum VGT_DMA_BUF_TYPE {
14255  * VGT_OUTPATH_SELECT enum
14258 typedef enum VGT_OUTPATH_SELECT {
14269  * VGT_GRP_PRIM_TYPE enum
14272 typedef enum VGT_GRP_PRIM_TYPE {
14295  * VGT_GRP_PRIM_ORDER enum
14298 typedef enum VGT_GRP_PRIM_ORDER {
14307  * VGT_GROUP_CONV_SEL enum
14310 typedef enum VGT_GROUP_CONV_SEL {
14323  * VGT_GS_MODE_TYPE enum
14326 typedef enum VGT_GS_MODE_TYPE {
14336  * VGT_GS_CUT_MODE enum
14339 typedef enum VGT_GS_CUT_MODE {
14347  * VGT_GS_OUTPRIM_TYPE enum
14350 typedef enum VGT_GS_OUTPRIM_TYPE {
14358  * VGT_CACHE_INVALID_MODE enum
14361 typedef enum VGT_CACHE_INVALID_MODE {
14368  * VGT_TESS_TYPE enum
14371 typedef enum VGT_TESS_TYPE {
14378  * VGT_TESS_PARTITION enum
14381 typedef enum VGT_TESS_PARTITION {
14389  * VGT_TESS_TOPOLOGY enum
14392 typedef enum VGT_TESS_TOPOLOGY {
14400  * VGT_RDREQ_POLICY enum
14403 typedef enum VGT_RDREQ_POLICY {
14410  * VGT_DIST_MODE enum
14413 typedef enum VGT_DIST_MODE {
14421  * VGT_DETECT_ONE enum
14424 typedef enum VGT_DETECT_ONE {
14431  * VGT_DETECT_ZERO enum
14434 typedef enum VGT_DETECT_ZERO {
14441  * VGT_STAGES_LS_EN enum
14444 typedef enum VGT_STAGES_LS_EN {
14452  * VGT_STAGES_HS_EN enum
14455 typedef enum VGT_STAGES_HS_EN {
14461  * VGT_STAGES_ES_EN enum
14464 typedef enum VGT_STAGES_ES_EN {
14472  * VGT_STAGES_GS_EN enum
14475 typedef enum VGT_STAGES_GS_EN {
14481  * VGT_STAGES_VS_EN enum
14484 typedef enum VGT_STAGES_VS_EN {
14492  * GE_PERFCOUNT_SELECT enum
14495 typedef enum GE_PERFCOUNT_SELECT {
14675  * WD_IA_DRAW_TYPE enum
14678 typedef enum WD_IA_DRAW_TYPE {
14690  * WD_IA_DRAW_REG_XFER enum
14693 typedef enum WD_IA_DRAW_REG_XFER {
14701  * WD_IA_DRAW_SOURCE enum
14704 typedef enum WD_IA_DRAW_SOURCE {
14722  * GB_EDC_DED_MODE enum
14725 typedef enum GB_EDC_DED_MODE {
14736  * CHA_PERF_SEL enum
14739 typedef enum CHA_PERF_SEL {
14783  * CHC_PERF_SEL enum
14786 typedef enum CHC_PERF_SEL {
14797  * CHCG_PERF_SEL enum
14800 typedef enum CHCG_PERF_SEL {
14811  * GL1A_PERF_SEL enum
14814 typedef enum GL1A_PERF_SEL {
14857  * GL1C_PERF_SEL enum
14860 typedef enum GL1C_PERF_SEL {
14871  * GL1CG_PERF_SEL enum
14874 typedef enum GL1CG_PERF_SEL {
14889  * TA_TC_REQ_MODES enum
14892 typedef enum TA_TC_REQ_MODES {
14904  * TA_TC_ADDR_MODES enum
14907 typedef enum TA_TC_ADDR_MODES {
14918  * TA_PERFCOUNT_SEL enum
14921 typedef enum TA_PERFCOUNT_SEL {
15044  * TD_PERFCOUNT_SEL enum
15047 typedef enum TD_PERFCOUNT_SEL {
15110  * TCP_PERFCOUNT_SELECT enum
15113 typedef enum TCP_PERFCOUNT_SELECT {
15214  * TCP_CACHE_POLICIES enum
15217 typedef enum TCP_CACHE_POLICIES {
15225  * TCP_CACHE_STORE_POLICIES enum
15228 typedef enum TCP_CACHE_STORE_POLICIES {
15234  * TCP_WATCH_MODES enum
15237 typedef enum TCP_WATCH_MODES {
15245  * TCP_DSM_DATA_SEL enum
15248 typedef enum TCP_DSM_DATA_SEL {
15256  * TCP_DSM_SINGLE_WRITE enum
15259 typedef enum TCP_DSM_SINGLE_WRITE {
15265  * TCP_DSM_INJECT_SEL enum
15268 typedef enum TCP_DSM_INJECT_SEL {
15276  * TCP_OPCODE_TYPE enum
15279 typedef enum TCP_OPCODE_TYPE {
15293  * GL2C_PERF_SEL enum
15296 typedef enum GL2C_PERF_SEL {
15528  * GL2A_PERF_SEL enum
15531 typedef enum GL2A_PERF_SEL {
15598  * GRBM_PERF_SEL enum
15601 typedef enum GRBM_PERF_SEL {
15651  * GRBM_SE0_PERF_SEL enum
15654 typedef enum GRBM_SE0_PERF_SEL {
15677  * GRBM_SE1_PERF_SEL enum
15680 typedef enum GRBM_SE1_PERF_SEL {
15703  * GRBM_SE2_PERF_SEL enum
15706 typedef enum GRBM_SE2_PERF_SEL {
15729  * GRBM_SE3_PERF_SEL enum
15732 typedef enum GRBM_SE3_PERF_SEL {
15759  * CP_RING_ID enum
15762 typedef enum CP_RING_ID {
15770  * CP_PIPE_ID enum
15773 typedef enum CP_PIPE_ID {
15781  * CP_ME_ID enum
15784 typedef enum CP_ME_ID {
15792  * SPM_PERFMON_STATE enum
15795 typedef enum SPM_PERFMON_STATE {
15805  * CP_PERFMON_STATE enum
15808 typedef enum CP_PERFMON_STATE {
15818  * CP_PERFMON_ENABLE_MODE enum
15821 typedef enum CP_PERFMON_ENABLE_MODE {
15829  * CPG_PERFCOUNT_SEL enum
15832 typedef enum CPG_PERFCOUNT_SEL {
15914  * CPF_PERFCOUNT_SEL enum
15917 typedef enum CPF_PERFCOUNT_SEL {
15961  * CPC_PERFCOUNT_SEL enum
15964 typedef enum CPC_PERFCOUNT_SEL {
16013  * CP_ALPHA_TAG_RAM_SEL enum
16016 typedef enum CP_ALPHA_TAG_RAM_SEL {
16024  * CPF_PERFCOUNTWINDOW_SEL enum
16027 typedef enum CPF_PERFCOUNTWINDOW_SEL {
16036  * CPG_PERFCOUNTWINDOW_SEL enum
16039 typedef enum CPG_PERFCOUNTWINDOW_SEL {
16074  * CPF_LATENCY_STATS_SEL enum
16077 typedef enum CPF_LATENCY_STATS_SEL {
16093  * CPG_LATENCY_STATS_SEL enum
16096 typedef enum CPG_LATENCY_STATS_SEL {
16118  * CPC_LATENCY_STATS_SEL enum
16121 typedef enum CPC_LATENCY_STATS_SEL {
16134  * CP_DDID_CNTL_MODE enum
16137 typedef enum CP_DDID_CNTL_MODE {
16143  * CP_DDID_CNTL_SIZE enum
16146 typedef enum CP_DDID_CNTL_SIZE {
16152  * CP_DDID_CNTL_VMID_SEL enum
16155 typedef enum CP_DDID_CNTL_VMID_SEL {
16240  * SX_BLEND_OPT enum
16243 typedef enum SX_BLEND_OPT {
16255  * SX_OPT_COMB_FCN enum
16258 typedef enum SX_OPT_COMB_FCN {
16270  * SX_DOWNCONVERT_FORMAT enum
16273 typedef enum SX_DOWNCONVERT_FORMAT {
16288  * SX_PERFCOUNTER_VALS enum
16291 typedef enum SX_PERFCOUNTER_VALS {
16520  * ForceControl enum
16523 typedef enum ForceControl {
16531  * ZSamplePosition enum
16534 typedef enum ZSamplePosition {
16540  * ZOrder enum
16543 typedef enum ZOrder {
16551  * ZpassControl enum
16554 typedef enum ZpassControl {
16561  * ZModeForce enum
16564 typedef enum ZModeForce {
16572  * ZLimitSumm enum
16575 typedef enum ZLimitSumm {
16583  * CompareFrag enum
16586 typedef enum CompareFrag {
16598  * StencilOp enum
16601 typedef enum StencilOp {
16621  * ConservativeZExport enum
16624 typedef enum ConservativeZExport {
16632  * DbPSLControl enum
16635 typedef enum DbPSLControl {
16643  * DbPRTFaultBehavior enum
16646 typedef enum DbPRTFaultBehavior {
16654  * PerfCounter_Vals enum
16657 typedef enum PerfCounter_Vals {
17007  * RingCounterControl enum
17010 typedef enum RingCounterControl {
17017  * DbMemArbWatermarks enum
17020 typedef enum DbMemArbWatermarks {
17032  * DFSMFlushEvents enum
17035 typedef enum DFSMFlushEvents {
17050  * PixelPipeCounterId enum
17053 typedef enum PixelPipeCounterId {
17065  * PixelPipeStride enum
17068 typedef enum PixelPipeStride {
17076  * FullTileWaveBreak enum
17079 typedef enum FullTileWaveBreak {
17091  * TEX_BORDER_COLOR_TYPE enum
17094 typedef enum TEX_BORDER_COLOR_TYPE {
17102  * TEX_BC_SWIZZLE enum
17105 typedef enum TEX_BC_SWIZZLE {
17115  * TEX_CHROMA_KEY enum
17118 typedef enum TEX_CHROMA_KEY {
17126  * TEX_CLAMP enum
17129 typedef enum TEX_CLAMP {
17141  * TEX_COORD_TYPE enum
17144 typedef enum TEX_COORD_TYPE {
17150  * TEX_DEPTH_COMPARE_FUNCTION enum
17153 typedef enum TEX_DEPTH_COMPARE_FUNCTION {
17165  * TEX_DIM enum
17168 typedef enum TEX_DIM {
17180  * TEX_FORMAT_COMP enum
17183 typedef enum TEX_FORMAT_COMP {
17191  * TEX_MAX_ANISO_RATIO enum
17194 typedef enum TEX_MAX_ANISO_RATIO {
17206  * TEX_MIP_FILTER enum
17209 typedef enum TEX_MIP_FILTER {
17217  * TEX_REQUEST_SIZE enum
17220 typedef enum TEX_REQUEST_SIZE {
17228  * TEX_SAMPLER_TYPE enum
17231 typedef enum TEX_SAMPLER_TYPE {
17237  * TEX_XY_FILTER enum
17240 typedef enum TEX_XY_FILTER {
17248  * TEX_Z_FILTER enum
17251 typedef enum TEX_Z_FILTER {
17259  * VTX_CLAMP enum
17262 typedef enum VTX_CLAMP {
17268  * VTX_FETCH_TYPE enum
17271 typedef enum VTX_FETCH_TYPE {
17279  * VTX_FORMAT_COMP_ALL enum
17282 typedef enum VTX_FORMAT_COMP_ALL {
17288  * VTX_MEM_REQUEST_SIZE enum
17291 typedef enum VTX_MEM_REQUEST_SIZE {
17297  * TVX_DATA_FORMAT enum
17300 typedef enum TVX_DATA_FORMAT {
17368  * TVX_DST_SEL enum
17371 typedef enum TVX_DST_SEL {
17383  * TVX_ENDIAN_SWAP enum
17386 typedef enum TVX_ENDIAN_SWAP {
17394  * TVX_INST enum
17397 typedef enum TVX_INST {
17433  * TVX_NUM_FORMAT_ALL enum
17436 typedef enum TVX_NUM_FORMAT_ALL {
17444  * TVX_SRC_SEL enum
17447 typedef enum TVX_SRC_SEL {
17457  * TVX_SRF_MODE_ALL enum
17460 typedef enum TVX_SRF_MODE_ALL {
17466  * TVX_TYPE enum
17469 typedef enum TVX_TYPE {
17481  * PH_PERFCNT_SEL enum
17484 typedef enum PH_PERFCNT_SEL {
18448  * SU_PERFCNT_SEL enum
18451 typedef enum SU_PERFCNT_SEL {
18882  * SC_PERFCNT_SEL enum
18885 typedef enum SC_PERFCNT_SEL {
19390  * SePairXsel enum
19393 typedef enum SePairXsel {
19401  * SePairYsel enum
19404 typedef enum SePairYsel {
19412  * SePairMap enum
19415 typedef enum SePairMap {
19423  * SeXsel enum
19426 typedef enum SeXsel {
19434  * SeYsel enum
19437 typedef enum SeYsel {
19445  * SeMap enum
19448 typedef enum SeMap {
19456  * ScXsel enum
19459 typedef enum ScXsel {
19467  * ScYsel enum
19470 typedef enum ScYsel {
19478  * ScMap enum
19481 typedef enum ScMap {
19489  * PkrXsel2 enum
19492 typedef enum PkrXsel2 {
19500  * PkrXsel enum
19503 typedef enum PkrXsel {
19511  * PkrYsel enum
19514 typedef enum PkrYsel {
19522  * PkrMap enum
19525 typedef enum PkrMap {
19533  * RbXsel enum
19536 typedef enum RbXsel {
19542  * RbYsel enum
19545 typedef enum RbYsel {
19551  * RbXsel2 enum
19554 typedef enum RbXsel2 {
19562  * RbMap enum
19565 typedef enum RbMap {
19573  * BinningMode enum
19576 typedef enum BinningMode {
19584  * BinSizeExtend enum
19587 typedef enum BinSizeExtend {
19596  * BinMapMode enum
19599 typedef enum BinMapMode {
19606  * BinEventCntl enum
19609 typedef enum BinEventCntl {
19617  * CovToShaderSel enum
19620 typedef enum CovToShaderSel {
19628  * ScUncertaintyRegionMode enum
19631 typedef enum ScUncertaintyRegionMode {
19642  * RMIPerfSel enum
19645 typedef enum RMIPerfSel {
19910  * GCRPerfSel enum
19913 typedef enum GCRPerfSel {
20015  * UTCL1PerfSel enum
20018 typedef enum UTCL1PerfSel {
20041  * SDMA_PERF_SEL enum
20044 typedef enum SDMA_PERF_SEL {
20146  * NUM_PIPES_BC_ENUM enum
20149 typedef enum NUM_PIPES_BC_ENUM {
20155  * NUM_BANKS_BC_ENUM enum
20158 typedef enum NUM_BANKS_BC_ENUM {
20167  * SWIZZLE_TYPE_ENUM enum
20170 typedef enum SWIZZLE_TYPE_ENUM {
20179  * TC_MICRO_TILE_MODE enum
20182 typedef enum TC_MICRO_TILE_MODE {
20193  * SWIZZLE_MODE_ENUM enum
20196 typedef enum SWIZZLE_MODE_ENUM {
20232  * SurfaceEndian enum
20235 typedef enum SurfaceEndian {
20243  * ArrayMode enum
20246 typedef enum ArrayMode {
20266  * NumPipes enum
20269 typedef enum NumPipes {
20280  * NumBanksConfig enum
20283 typedef enum NumBanksConfig {
20292  * PipeInterleaveSize enum
20295 typedef enum PipeInterleaveSize {
20303  * BankInterleaveSize enum
20306 typedef enum BankInterleaveSize {
20314  * NumShaderEngines enum
20317 typedef enum NumShaderEngines {
20325  * NumRbPerShaderEngine enum
20328 typedef enum NumRbPerShaderEngine {
20335  * NumGPUs enum
20338 typedef enum NumGPUs {
20346  * NumMaxCompressedFragments enum
20349 typedef enum NumMaxCompressedFragments {
20357  * ShaderEngineTileSize enum
20360 typedef enum ShaderEngineTileSize {
20366  * MultiGPUTileSize enum
20369 typedef enum MultiGPUTileSize {
20377  * RowSize enum
20380 typedef enum RowSize {
20387  * NumLowerPipes enum
20390 typedef enum NumLowerPipes {
20396  * ColorTransform enum
20399 typedef enum ColorTransform {
20407  * CompareRef enum
20410 typedef enum CompareRef {
20422  * ReadSize enum
20425 typedef enum ReadSize {
20431  * DepthFormat enum
20434 typedef enum DepthFormat {
20446  * ZFormat enum
20449 typedef enum ZFormat {
20457  * StencilFormat enum
20460 typedef enum StencilFormat {
20466  * CmaskMode enum
20469 typedef enum CmaskMode {
20489  * QuadExportFormat enum
20492 typedef enum QuadExportFormat {
20508  * QuadExportFormatOld enum
20511 typedef enum QuadExportFormatOld {
20521  * ColorFormat enum
20524 typedef enum ColorFormat {
20560  * SurfaceFormat enum
20563 typedef enum SurfaceFormat {
20631  * IMG_NUM_FORMAT_FMASK enum
20634 typedef enum IMG_NUM_FORMAT_FMASK {
20654  * IMG_NUM_FORMAT_N_IN_16 enum
20657 typedef enum IMG_NUM_FORMAT_N_IN_16 {
20677  * TileType enum
20680 typedef enum TileType {
20686  * NonDispTilingOrder enum
20689 typedef enum NonDispTilingOrder {
20695  * MicroTileMode enum
20698 typedef enum MicroTileMode {
20707  * TileSplit enum
20710 typedef enum TileSplit {
20721  * SampleSplit enum
20724 typedef enum SampleSplit {
20732  * PipeConfig enum
20735 typedef enum PipeConfig {
20758  * SeEnable enum
20761 typedef enum SeEnable {
20767  * NumBanks enum
20770 typedef enum NumBanks {
20778  * BankWidth enum
20781 typedef enum BankWidth {
20789  * BankHeight enum
20792 typedef enum BankHeight {
20800  * BankWidthHeight enum
20803 typedef enum BankWidthHeight {
20811  * MacroTileAspect enum
20814 typedef enum MacroTileAspect {
20822  * PipeTiling enum
20825 typedef enum PipeTiling {
20833  * BankTiling enum
20836 typedef enum BankTiling {
20842  * GroupInterleave enum
20845 typedef enum GroupInterleave {
20851  * RowTiling enum
20854 typedef enum RowTiling {
20866  * BankSwapBytes enum
20869 typedef enum BankSwapBytes {
20877  * SampleSplitBytes enum
20880 typedef enum SampleSplitBytes {
20888  * SurfaceNumber enum
20891 typedef enum SurfaceNumber {
20903  * SurfaceSwap enum
20906 typedef enum SurfaceSwap {
20914  * RoundMode enum
20917 typedef enum RoundMode {
20923  * BUF_FMT enum
20926 typedef enum BUF_FMT {
21058  * IMG_FMT enum
21061 typedef enum IMG_FMT {
21495  * BUF_DATA_FORMAT enum
21498 typedef enum BUF_DATA_FORMAT {
21518  * IMG_DATA_FORMAT enum
21521 typedef enum IMG_DATA_FORMAT {
21642  * BUF_NUM_FORMAT enum
21645 typedef enum BUF_NUM_FORMAT {
21657  * IMG_NUM_FORMAT enum
21660 typedef enum IMG_NUM_FORMAT {
21684  * IH_PERF_SEL enum
21687 typedef enum IH_PERF_SEL {
22409  * IH_CLIENT_TYPE enum
22412 typedef enum IH_CLIENT_TYPE {
22420  * IH_RING_ID enum
22423 typedef enum IH_RING_ID {
22431  * IH_VF_RB_SELECT enum
22434 typedef enum IH_VF_RB_SELECT {
22442  * IH_INTERFACE_TYPE enum
22445 typedef enum IH_INTERFACE_TYPE {
22455  * SEM_PERF_SEL enum
22458 typedef enum SEM_PERF_SEL {
22651  * EFC_SURFACE_PIXEL_FORMAT enum
22654 typedef enum EFC_SURFACE_PIXEL_FORMAT {
22736  * UVDFirmwareCommand enum
22739 typedef enum UVDFirmwareCommand {