Lines Matching full:and
4 # Licensed and distributed under the GPL
13 tristate "EDAC (Error Detection And Correction) reporting"
40 levels are 0-4 (from low to high) and by default it is set to 2.
69 It should be noticed that keeping both GHES and a hardware-driven
84 Support for error detection and correction of DRAM ECC errors on
90 AMD CPUs up to and excluding family 0x17 provide for Memory
92 module allows the operator/user to inject Uncorrectable and
102 In addition, there are two control files, inject_read and inject_write,
103 which trigger the DRAM ECC Read and Write respectively.
109 Support for error detection and correction for Amazon's Annapurna
110 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
116 Support for error detection and correction on the AMD 76x
123 Support for error detection and correction on the Intel
124 E7205, E7500, E7501 and E7505 server chipsets.
127 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
130 Support for error detection and correction on the Intel
138 Support for error detection and correction on the Intel
145 Support for error detection and correction on the Intel
146 DP82785P and E7210 server chipsets.
152 Support for error detection and correction on the Intel
159 Support for error detection and correction on the Intel
160 3000 and 3010 server chipsets.
166 Support for error detection and correction on the Intel
167 3200 and 3210 server chipsets.
173 Support for error detection and correction on the Intel
180 Support for error detection and correction on the Intel
187 Support for error detection and correction the Intel
194 Support for error detection and correction the Intel
197 and Xeon 55xx processors.
203 Support for error detection and correction on the Intel
210 Support for error detection and correction on the Radisys
218 Support for error detection and correction the Intel
225 Support for error detection and correction the Intel
232 Support for error detection and correction the Intel
239 Support for error detection and correction the Intel
240 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
249 Support for error detection and correction the Intel
261 Support for error detection and correction the Intel
271 Support for error detection and correction on the Intel
273 first used on the Apollo Lake platform and Denverton
281 Support for error detection and correction on the Intel
290 Support for error detection and correction on the Freescale
297 Support for error detection and correction on Freescale memory
304 Support for error detection and correction on PA Semi
311 Support for error detection and correction on the
312 IBM CPC925 Bridge and Memory Controller, which is
320 Support for error detection and correction on the
327 Support for error detection and correction on the
334 Support for error detection and correction on the primary caches of
341 Support for error detection and correction on the
348 Support for error detection and correction on the
355 Support for error detection and correction on the
363 Support for error detection and correction on the
365 Coherent Processor Interconnect (CCPI) and L2 cache
372 Support for error detection and correction on the
380 Support for error detection and correction on the
389 Support for error detection and correction on the
397 Support for error detection and correction on the
404 Support for error detection and correction on the
411 Support for error detection and correction on the
418 Support for error detection and correction on the
425 Support for error detection and correction on the
432 Support for error detection and correction on the
439 Support for error detection and correction on the
446 Support for error detection and correction on the SiFive SoCs.
449 bool "Marvell Armada XP DDR and L2 Cache ECC"
452 Support for error correction and detection on the Marvell Aramada XP
453 DDR RAM and L2 cache controllers.
459 Support for error detection and correction on the Synopsys DDR
466 Support for error detection and correction on the
473 Support for error detection and correction on the TI SoCs.
479 Support for error detection and correction on the
482 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
484 of Tag RAM and Data RAM.
486 For debugging issues having to do with stability and overall system
493 Support for error detection and correction on the Aspeed AST BMC SoC.
502 Support for error detection and correction on the
509 Support for error detection and correction on the
516 This driver supports error detection and correction for the
524 Support for error detection and correction on the Nuvoton NPCM DDR
535 Support for error detection and correction on the Xilinx Versal DDR
538 Report both single bit errors (CE) and double bit errors (UE).
539 Support injecting both correctable and uncorrectable errors
546 Support for error detection and correction on the Loongson