Lines Matching full:list

106 /* register a list of aliases */
108 const struct samsung_clock_alias *list, in samsung_clk_register_alias() argument
114 for (idx = 0; idx < nr_clk; idx++, list++) { in samsung_clk_register_alias()
115 if (!list->id) { in samsung_clk_register_alias()
121 clk_hw = ctx->clk_data.hws[list->id]; in samsung_clk_register_alias()
124 list->id); in samsung_clk_register_alias()
128 ret = clk_hw_register_clkdev(clk_hw, list->alias, in samsung_clk_register_alias()
129 list->dev_name); in samsung_clk_register_alias()
132 __func__, list->alias); in samsung_clk_register_alias()
136 /* register a list of fixed clocks */
138 const struct samsung_fixed_rate_clock *list, in samsung_clk_register_fixed_rate() argument
144 for (idx = 0; idx < nr_clk; idx++, list++) { in samsung_clk_register_fixed_rate()
145 clk_hw = clk_hw_register_fixed_rate(ctx->dev, list->name, in samsung_clk_register_fixed_rate()
146 list->parent_name, list->flags, list->fixed_rate); in samsung_clk_register_fixed_rate()
149 list->name); in samsung_clk_register_fixed_rate()
153 samsung_clk_add_lookup(ctx, clk_hw, list->id); in samsung_clk_register_fixed_rate()
157 /* register a list of fixed factor clocks */
159 const struct samsung_fixed_factor_clock *list, unsigned int nr_clk) in samsung_clk_register_fixed_factor() argument
164 for (idx = 0; idx < nr_clk; idx++, list++) { in samsung_clk_register_fixed_factor()
165 clk_hw = clk_hw_register_fixed_factor(ctx->dev, list->name, in samsung_clk_register_fixed_factor()
166 list->parent_name, list->flags, list->mult, list->div); in samsung_clk_register_fixed_factor()
169 list->name); in samsung_clk_register_fixed_factor()
173 samsung_clk_add_lookup(ctx, clk_hw, list->id); in samsung_clk_register_fixed_factor()
177 /* register a list of mux clocks */
179 const struct samsung_mux_clock *list, in samsung_clk_register_mux() argument
185 for (idx = 0; idx < nr_clk; idx++, list++) { in samsung_clk_register_mux()
186 clk_hw = clk_hw_register_mux(ctx->dev, list->name, in samsung_clk_register_mux()
187 list->parent_names, list->num_parents, list->flags, in samsung_clk_register_mux()
188 ctx->reg_base + list->offset, in samsung_clk_register_mux()
189 list->shift, list->width, list->mux_flags, &ctx->lock); in samsung_clk_register_mux()
192 list->name); in samsung_clk_register_mux()
196 samsung_clk_add_lookup(ctx, clk_hw, list->id); in samsung_clk_register_mux()
200 /* register a list of div clocks */
202 const struct samsung_div_clock *list, in samsung_clk_register_div() argument
208 for (idx = 0; idx < nr_clk; idx++, list++) { in samsung_clk_register_div()
209 if (list->table) in samsung_clk_register_div()
211 list->name, list->parent_name, list->flags, in samsung_clk_register_div()
212 ctx->reg_base + list->offset, in samsung_clk_register_div()
213 list->shift, list->width, list->div_flags, in samsung_clk_register_div()
214 list->table, &ctx->lock); in samsung_clk_register_div()
216 clk_hw = clk_hw_register_divider(ctx->dev, list->name, in samsung_clk_register_div()
217 list->parent_name, list->flags, in samsung_clk_register_div()
218 ctx->reg_base + list->offset, list->shift, in samsung_clk_register_div()
219 list->width, list->div_flags, &ctx->lock); in samsung_clk_register_div()
222 list->name); in samsung_clk_register_div()
226 samsung_clk_add_lookup(ctx, clk_hw, list->id); in samsung_clk_register_div()
230 /* register a list of gate clocks */
232 const struct samsung_gate_clock *list, in samsung_clk_register_gate() argument
238 for (idx = 0; idx < nr_clk; idx++, list++) { in samsung_clk_register_gate()
239 clk_hw = clk_hw_register_gate(ctx->dev, list->name, list->parent_name, in samsung_clk_register_gate()
240 list->flags, ctx->reg_base + list->offset, in samsung_clk_register_gate()
241 list->bit_idx, list->gate_flags, &ctx->lock); in samsung_clk_register_gate()
244 list->name); in samsung_clk_register_gate()
248 samsung_clk_add_lookup(ctx, clk_hw, list->id); in samsung_clk_register_gate()
358 * for each CMU. It also add CMU register list to register cache.