Lines Matching full:gate
1109 GATE(CLK_GOUT_CMU_DROOPDETECTOR, "gout_droopdetector",
1112 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",
1114 GATE(CLK_GOUT_CMU_ABOX_CPUABOX, "gout_cmu_abox_cpuabox",
1117 GATE(CLK_GOUT_CMU_APM_BUS, "gout_cmu_apm_bus", "mout_cmu_apm_bus",
1119 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1121 GATE(CLK_GOUT_CMU_BUSC_BUS, "gout_cmu_busc_bus", "mout_cmu_busc_bus",
1123 GATE(CLK_GOUT_CMU_BUSC_BUSPHSI2C, "gout_cmu_busc_busphsi2c",
1126 GATE(CLK_GOUT_CMU_CAM_BUS, "gout_cmu_cam_bus", "mout_cmu_cam_bus",
1128 GATE(CLK_GOUT_CMU_CAM_TPU0, "gout_cmu_cam_tpu0", "mout_cmu_cam_tpu0",
1130 GATE(CLK_GOUT_CMU_CAM_TPU1, "gout_cmu_cam_tpu1", "mout_cmu_cam_tpu1",
1132 GATE(CLK_GOUT_CMU_CAM_VRA, "gout_cmu_cam_vra", "mout_cmu_cam_vra",
1134 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
1136 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1138 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1140 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1142 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_core_bus",
1144 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
1147 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
1150 GATE(CLK_GOUT_CMU_DBG_BUS, "gout_cmu_dbg_bus", "mout_cmu_dbg_bus",
1152 GATE(CLK_GOUT_CMU_DCAM_BUS, "gout_cmu_dcam_bus", "mout_cmu_dcam_bus",
1154 GATE(CLK_GOUT_CMU_DCAM_IMGD, "gout_cmu_dcam_imgd",
1157 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
1159 GATE(CLK_GOUT_CMU_DSP_BUS, "gout_cmu_dsp_bus", "mout_cmu_dsp_bus",
1161 GATE(CLK_GOUT_CMU_FSYS0_BUS, "gout_cmu_fsys0_bus", "mout_fsys0_bus",
1163 GATE(CLK_GOUT_CMU_FSYS0_DPGTC, "gout_cmu_fsys0_dpgtc",
1166 GATE(CLK_GOUT_CMU_FSYS0_MMC_EMBD, "gout_cmu_fsys0_mmc_embd",
1169 GATE(CLK_GOUT_CMU_FSYS0_UFS_EMBD, "gout_cmu_fsys0_ufs_embd",
1172 GATE(CLK_GOUT_CMU_FSYS0_USBDRD30, "gout_cmu_fsys0_usbdrd30",
1175 GATE(CLK_GOUT_CMU_FSYS1_BUS, "gout_cmu_fsys1_bus",
1178 GATE(CLK_GOUT_CMU_FSYS1_MMC_CARD, "gout_cmu_fsys1_mmc_card",
1181 GATE(CLK_GOUT_CMU_FSYS1_PCIE, "gout_cmu_fsys1_pcie",
1184 GATE(CLK_GOUT_CMU_FSYS1_UFS_CARD, "gout_cmu_fsys1_ufs_card",
1187 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
1189 GATE(CLK_GOUT_CMU_G2D_JPEG, "gout_cmu_g2d_jpeg", "mout_cmu_g2d_jpeg",
1191 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",
1193 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
1195 GATE(CLK_GOUT_CMU_IMEM_BUS, "gout_cmu_imem_bus", "mout_cmu_imem_bus",
1197 GATE(CLK_GOUT_CMU_ISPHQ_BUS, "gout_cmu_isphq_bus",
1200 GATE(CLK_GOUT_CMU_ISPLP_BUS, "gout_cmu_isplp_bus",
1203 GATE(CLK_GOUT_CMU_IVA_BUS, "gout_cmu_iva_bus", "mout_cmu_iva_bus",
1205 GATE(CLK_GOUT_CMU_MFC_BUS, "gout_cmu_mfc_bus", "mout_cmu_mfc_bus",
1207 GATE(CLK_GOUT_CMU_MODEM_SHARED0, "gout_cmu_modem_shared0",
1210 GATE(CLK_GOUT_CMU_MODEM_SHARED1, "gout_cmu_modem_shared1",
1213 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",
1216 GATE(CLK_GOUT_CMU_PERIC0_UART_DBG, "gout_cmu_peric0_uart_dbg",
1219 GATE(CLK_GOUT_CMU_PERIC0_USI00, "gout_cmu_peric0_usi00",
1222 GATE(CLK_GOUT_CMU_PERIC0_USI01, "gout_cmu_peric0_usi01",
1225 GATE(CLK_GOUT_CMU_PERIC0_USI02, "gout_cmu_peric0_usi02",
1228 GATE(CLK_GOUT_CMU_PERIC0_USI03, "gout_cmu_peric0_usi03",
1231 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",
1234 GATE(CLK_GOUT_CMU_PERIC1_SPEEDY2, "gout_cmu_peric1_speedy2",
1237 GATE(CLK_GOUT_CMU_PERIC1_SPI_CAM0, "gout_cmu_peric1_spi_cam0",
1240 GATE(CLK_GOUT_CMU_PERIC1_SPI_CAM1, "gout_cmu_peric1_spi_cam1",
1243 GATE(CLK_GOUT_CMU_PERIC1_UART_BT, "gout_cmu_peric1_uart_bt",
1246 GATE(CLK_GOUT_CMU_PERIC1_USI04, "gout_cmu_peric1_usi04",
1249 GATE(CLK_GOUT_CMU_PERIC1_USI05, "gout_cmu_peric1_usi05",
1252 GATE(CLK_GOUT_CMU_PERIC1_USI06, "gout_cmu_peric1_usi06",
1255 GATE(CLK_GOUT_CMU_PERIC1_USI07, "gout_cmu_peric1_usi07",
1258 GATE(CLK_GOUT_CMU_PERIC1_USI08, "gout_cmu_peric1_usi08",
1261 GATE(CLK_GOUT_CMU_PERIC1_USI09, "gout_cmu_peric1_usi09",
1264 GATE(CLK_GOUT_CMU_PERIC1_USI10, "gout_cmu_peric1_usi10",
1267 GATE(CLK_GOUT_CMU_PERIC1_USI11, "gout_cmu_peric1_usi11",
1270 GATE(CLK_GOUT_CMU_PERIC1_USI12, "gout_cmu_peric1_usi12",
1273 GATE(CLK_GOUT_CMU_PERIC1_USI13, "gout_cmu_peric1_usi13",
1276 GATE(CLK_GOUT_CMU_PERIS_BUS, "gout_cmu_peris_bus",
1279 GATE(CLK_GOUT_CMU_SRDZ_BUS, "gout_cmu_srdz_bus", "mout_cmu_srdz_bus",
1281 GATE(CLK_GOUT_CMU_SRDZ_IMGD, "gout_cmu_srdz_imgd",
1284 GATE(CLK_GOUT_CMU_VPU_BUS, "gout_cmu_vpu_bus", "mout_cmu_vpu_bus",
1406 GATE(CLK_GOUT_PERIS_CMU_PERIS_PCLK, "gout_peris_cmu_peris_pclk",
1410 GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM,
1414 GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKS,
1418 GATE(CLK_GOUT_PERIS_AXI2APB_PERISP0_ACLK,
1422 GATE(CLK_GOUT_PERIS_AXI2APB_PERISP1_ACLK,
1426 GATE(CLK_GOUT_PERIS_BUSIF_TMU_PCLK, "gout_peris_busif_tmu_pclk",
1431 GATE(CLK_GOUT_PERIS_GIC_CLK, "gout_peris_gic_clk",
1435 GATE(CLK_GOUT_PERIS_LHM_AXI_P_PERIS_I_CLK,
1439 GATE(CLK_GOUT_PERIS_MCT_PCLK, "gout_peris_mct_pclk",
1442 GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK, "gout_peris_otp_con_bira_pclk",
1446 GATE(CLK_GOUT_PERIS_OTP_CON_TOP_PCLK, "gout_peris_otp_con_top_pclk",
1450 GATE(CLK_GOUT_PERIS_PMU_PERIS_PCLK, "gout_peris_pmu_peris_pclk",
1454 GATE(CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_BUSP_CLK,
1458 GATE(CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_GIC_CLK,
1462 GATE(CLK_GOUT_PERIS_SYSREG_PERIS_PCLK, "gout_peris_sysreg_peris_pclk",
1466 GATE(CLK_GOUT_PERIS_TZPC00_PCLK, "gout_peris_tzpc00_pclk",
1469 GATE(CLK_GOUT_PERIS_TZPC01_PCLK, "gout_peris_tzpc01_pclk",
1472 GATE(CLK_GOUT_PERIS_TZPC02_PCLK, "gout_peris_tzpc02_pclk",
1475 GATE(CLK_GOUT_PERIS_TZPC03_PCLK, "gout_peris_tzpc03_pclk",
1478 GATE(CLK_GOUT_PERIS_TZPC04_PCLK, "gout_peris_tzpc04_pclk",
1481 GATE(CLK_GOUT_PERIS_TZPC05_PCLK, "gout_peris_tzpc05_pclk",
1484 GATE(CLK_GOUT_PERIS_TZPC06_PCLK, "gout_peris_tzpc06_pclk",
1487 GATE(CLK_GOUT_PERIS_TZPC07_PCLK, "gout_peris_tzpc07_pclk",
1490 GATE(CLK_GOUT_PERIS_TZPC08_PCLK, "gout_peris_tzpc08_pclk",
1493 GATE(CLK_GOUT_PERIS_TZPC09_PCLK, "gout_peris_tzpc09_pclk",
1496 GATE(CLK_GOUT_PERIS_TZPC10_PCLK, "gout_peris_tzpc10_pclk",
1499 GATE(CLK_GOUT_PERIS_TZPC11_PCLK, "gout_peris_tzpc11_pclk",
1502 GATE(CLK_GOUT_PERIS_TZPC12_PCLK, "gout_peris_tzpc12_pclk",
1505 GATE(CLK_GOUT_PERIS_TZPC13_PCLK, "gout_peris_tzpc13_pclk",
1508 GATE(CLK_GOUT_PERIS_TZPC14_PCLK, "gout_peris_tzpc14_pclk",
1511 GATE(CLK_GOUT_PERIS_TZPC15_PCLK, "gout_peris_tzpc15_pclk",
1514 GATE(CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK, "gout_peris_wdt_cluster0_pclk",
1518 GATE(CLK_GOUT_PERIS_WDT_CLUSTER1_PCLK, "gout_peris_wdt_cluster1_pclk",
1522 GATE(CLK_GOUT_PERIS_XIU_P_PERIS_ACLK, "gout_peris_xiu_p_peris_aclk",
1676 GATE(CLK_GOUT_FSYS0_FSYS0_CMU_FSYS0_PCLK,
1680 GATE(CLK_GOUT_FSYS0_AHBBR_FSYS0_HCLK, "gout_fsys0_ahbbr_fsys0_hclk",
1684 GATE(CLK_GOUT_FSYS0_AXI2AHB_FSYS0_ACLK,
1688 GATE(CLK_GOUT_FSYS0_AXI2AHB_USB_FSYS0_ACLK,
1692 GATE(CLK_GOUT_FSYS0_AXI2APB_FSYS0_ACLK,
1696 GATE(CLK_GOUT_FSYS0_BTM_FSYS0_I_ACLK, "gout_fsys0_btm_fsys0_i_aclk",
1700 GATE(CLK_GOUT_FSYS0_BTM_FSYS0_I_PCLK, "gout_fsys0_btm_fsys0_i_pclk",
1704 GATE(CLK_GOUT_FSYS0_DP_LINK_I_GTC_EXT_CLK,
1708 GATE(CLK_GOUT_FSYS0_DP_LINK_I_PCLK, "gout_fsys0_dp_link_i_pclk",
1712 GATE(CLK_GOUT_FSYS0_ETR_MIU_I_ACLK, "gout_fsys0_etr_miu_i_aclk",
1715 GATE(CLK_GOUT_FSYS0_ETR_MIU_I_PCLK, "gout_fsys0_etr_miu_i_pclk",
1718 GATE(CLK_GOUT_FSYS0_GPIO_FSYS0_PCLK, "gout_fsys0_gpio_fsys0_pclk",
1722 GATE(CLK_GOUT_FSYS0_LHM_AXI_D_USBTV_I_CLK,
1726 GATE(CLK_GOUT_FSYS0_LHM_AXI_G_ETR_I_CLK,
1730 GATE(CLK_GOUT_FSYS0_LHM_AXI_P_FSYS0_I_CLK,
1734 GATE(CLK_GOUT_FSYS0_LHS_ACEL_D_FSYS0_I_CLK,
1738 GATE(CLK_GOUT_FSYS0_MMC_EMBD_I_ACLK, "gout_fsys0_mmc_embd_i_aclk",
1742 GATE(CLK_GOUT_FSYS0_MMC_EMBD_SDCLKIN, "gout_fsys0_mmc_embd_sdclkin",
1746 GATE(CLK_GOUT_FSYS0_PMU_FSYS0_PCLK, "gout_fsys0_pmu_fsys0_pclk",
1749 GATE(CLK_GOUT_FSYS0_BCM_FSYS0_ACLK, "gout_fsys0_bcm_fsys0_aclk",
1752 GATE(CLK_GOUT_FSYS0_BCM_FSYS0_PCLK, "gout_fsys0_bcm_fsys0_pclk",
1755 GATE(CLK_GOUT_FSYS0_RSTNSYNC_CLK_FSYS0_BUS_CLK,
1759 GATE(CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK, "gout_fsys0_sysreg_fsys0_pclk",
1763 GATE(CLK_GOUT_FSYS0_UFS_EMBD_I_ACLK, "gout_fsys0_ufs_embd_i_aclk",
1767 GATE(CLK_GOUT_FSYS0_UFS_EMBD_I_CLK_UNIPRO,
1771 GATE(CLK_GOUT_FSYS0_UFS_EMBD_I_FMP_CLK,
1775 GATE(CLK_GOUT_FSYS0_USBTV_I_USB30DRD_ACLK,
1779 GATE(CLK_GOUT_FSYS0_USBTV_I_USB30DRD_REF_CLK,
1783 GATE(CLK_GOUT_FSYS0_USBTV_I_USB30DRD_SUSPEND_CLK,
1788 GATE(CLK_GOUT_FSYS0_USBTV_I_USBTVH_AHB_CLK,
1792 GATE(CLK_GOUT_FSYS0_USBTV_I_USBTVH_CORE_CLK,
1796 GATE(CLK_GOUT_FSYS0_USBTV_I_USBTVH_XIU_CLK,
1800 GATE(CLK_GOUT_FSYS0_US_D_FSYS0_USB_ACLK,
1804 GATE(CLK_GOUT_FSYS0_XIU_D_FSYS0_ACLK, "gout_fsys0_xiu_d_fsys0_aclk",
1808 GATE(CLK_GOUT_FSYS0_XIU_D_FSYS0_USB_ACLK,
1812 GATE(CLK_GOUT_FSYS0_XIU_P_FSYS0_ACLK,
1955 GATE(CLK_GOUT_FSYS1_PCIE_PHY_REF_CLK_IN,
1959 GATE(CLK_GOUT_FSYS1_ADM_AHB_SSS_HCLKM, "gout_fsys1_adm_ahb_sss_hclkm",
1963 GATE(CLK_GOUT_FSYS1_AHBBR_FSYS1_HCLK, "gout_fsys1_ahbbr_fsys1_hclk",
1967 GATE(CLK_GOUT_FSYS1_AXI2AHB_FSYS1_ACLK,
1971 GATE(CLK_GOUT_FSYS1_AXI2APB_FSYS1P0_ACLK,
1975 GATE(CLK_GOUT_FSYS1_AXI2APB_FSYS1P1_ACLK,
1979 GATE(CLK_GOUT_FSYS1_BTM_FSYS1_I_ACLK, "gout_fsys1_btm_fsys1_i_aclk",
1983 GATE(CLK_GOUT_FSYS1_BTM_FSYS1_I_PCLK, "gout_fsys1_btm_fsys1_i_pclk",
1987 GATE(CLK_GOUT_FSYS1_FSYS1_CMU_FSYS1_PCLK,
1991 GATE(CLK_GOUT_FSYS1_GPIO_FSYS1_PCLK, "gout_fsys1_gpio_fsys1_pclk",
1995 GATE(CLK_GOUT_FSYS1_LHM_AXI_P_FSYS1_I_CLK,
1999 GATE(CLK_GOUT_FSYS1_LHS_ACEL_D_FSYS1_I_CLK,
2003 GATE(CLK_GOUT_FSYS1_MMC_CARD_I_ACLK, "gout_fsys1_mmc_card_i_aclk",
2007 GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
2011 GATE(CLK_GOUT_FSYS1_PCIE_DBI_ACLK_0, "gout_fsys1_pcie_dbi_aclk_0",
2015 GATE(CLK_GOUT_FSYS1_PCIE_DBI_ACLK_1, "gout_fsys1_pcie_dbi_aclk_1",
2019 GATE(CLK_GOUT_FSYS1_PCIE_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK,
2024 GATE(CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_0,
2028 GATE(CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_1,
2032 GATE(CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2037 GATE(CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK,
2042 GATE(CLK_GOUT_FSYS1_PCIE_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL,
2047 GATE(CLK_GOUT_FSYS1_PCIE_SLV_ACLK_0, "gout_fsys1_pcie_slv_aclk_0",
2051 GATE(CLK_GOUT_FSYS1_PCIE_SLV_ACLK_1, "gout_fsys1_pcie_slv_aclk_1",
2055 GATE(CLK_GOUT_FSYS1_PMU_FSYS1_PCLK, "gout_fsys1_pmu_fsys1_pclk",
2059 GATE(CLK_GOUT_FSYS1_BCM_FSYS1_ACLK, "gout_fsys1_bcm_fsys1_aclk",
2063 GATE(CLK_GOUT_FSYS1_BCM_FSYS1_PCLK, "gout_fsys1_bcm_fsys1_pclk",
2067 GATE(CLK_GOUT_FSYS1_RSTNSYNC_CLK_FSYS1_BUS_CLK,
2071 GATE(CLK_GOUT_FSYS1_RTIC_I_ACLK, "gout_fsys1_rtic_i_aclk",
2074 GATE(CLK_GOUT_FSYS1_RTIC_I_PCLK, "gout_fsys1_rtic_i_pclk",
2077 GATE(CLK_GOUT_FSYS1_SSS_I_ACLK, "gout_fsys1_sss_i_aclk",
2080 GATE(CLK_GOUT_FSYS1_SSS_I_PCLK, "gout_fsys1_sss_i_pclk",
2083 GATE(CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK, "gout_fsys1_sysreg_fsys1_pclk",
2087 GATE(CLK_GOUT_FSYS1_TOE_WIFI0_I_CLK, "gout_fsys1_toe_wifi0_i_clk",
2091 GATE(CLK_GOUT_FSYS1_TOE_WIFI1_I_CLK, "gout_fsys1_toe_wifi1_i_clk",
2095 GATE(CLK_GOUT_FSYS1_UFS_CARD_I_ACLK, "gout_fsys1_ufs_card_i_aclk",
2099 GATE(CLK_GOUT_FSYS1_UFS_CARD_I_CLK_UNIPRO,
2103 GATE(CLK_GOUT_FSYS1_UFS_CARD_I_FMP_CLK,
2107 GATE(CLK_GOUT_FSYS1_XIU_D_FSYS1_ACLK, "gout_fsys1_xiu_d_fsys1_aclk",
2111 GATE(CLK_GOUT_FSYS1_XIU_P_FSYS1_ACLK, "gout_fsys1_xiu_p_fsys1_aclk",
2231 GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK,
2235 GATE(CLK_GOUT_PERIC0_AXI2APB_PERIC0_ACLK,
2239 GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, "gout_peric0_gpio_peric0_pclk",
2243 GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK,
2247 GATE(CLK_GOUT_PERIC0_PMU_PERIC0_PCLK, "gout_peric0_pmu_peric0_pclk",
2251 GATE(CLK_GOUT_PERIC0_PWM_I_PCLK_S0, "gout_peric0_pwm_i_pclk_s0",
2255 GATE(CLK_GOUT_PERIC0_RSTNSYNC_CLK_PERIC0_BUSP_CLK,
2260 GATE(CLK_GOUT_PERIC0_SPEEDY2_TSP_CLK, "gout_peric0_speedy2_tsp_clk",
2264 GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK,
2268 GATE(CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK,
2272 GATE(CLK_GOUT_PERIC0_UART_DBG_PCLK, "gout_peric0_uart_dbg_pclk",
2276 GATE(CLK_GOUT_PERIC0_USI00_I_PCLK, "gout_peric0_usi00_i_pclk",
2279 GATE(CLK_GOUT_PERIC0_USI00_I_SCLK_USI, "gout_peric0_usi00_i_sclk_usi",
2283 GATE(CLK_GOUT_PERIC0_USI01_I_PCLK, "gout_peric0_usi01_i_pclk",
2286 GATE(CLK_GOUT_PERIC0_USI01_I_SCLK_USI, "gout_peric0_usi01_i_sclk_usi",
2290 GATE(CLK_GOUT_PERIC0_USI02_I_PCLK, "gout_peric0_usi02_i_pclk",
2293 GATE(CLK_GOUT_PERIC0_USI02_I_SCLK_USI, "gout_peric0_usi02_i_sclk_usi",
2297 GATE(CLK_GOUT_PERIC0_USI03_I_PCLK, "gout_peric0_usi03_i_pclk",
2300 GATE(CLK_GOUT_PERIC0_USI03_I_SCLK_USI, "gout_peric0_usi03_i_sclk_usi",
2561 GATE(CLK_GOUT_PERIC1_PERIC1_CMU_PERIC1_PCLK,
2565 GATE(CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_SPEEDY2_CLK,
2570 GATE(CLK_GOUT_PERIC1_AXI2APB_PERIC1P0_ACLK,
2575 GATE(CLK_GOUT_PERIC1_AXI2APB_PERIC1P1_ACLK,
2579 GATE(CLK_GOUT_PERIC1_AXI2APB_PERIC1P2_ACLK,
2583 GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK,
2587 GATE(CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK, "gout_peric1_hsi2c_cam0_ipclk",
2591 GATE(CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK,
2595 GATE(CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK,
2599 GATE(CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK, "gout_peric1_hsi2c_cam3_ipclk",
2603 GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK,
2607 GATE(CLK_GOUT_PERIC1_PMU_PERIC1_PCLK, "gout_peric1_pmu_peric1_pclk",
2611 GATE(CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_BUSP_CLK,
2616 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI1_CLK, "gout_peric1_speedy2_ddi1_clk",
2620 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI1_SCLK,
2624 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI2_CLK, "gout_peric1_speedy2_ddi2_clk",
2628 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI2_SCLK,
2632 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI_CLK, "gout_peric1_speedy2_ddi_clk",
2636 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI_SCLK, "gout_peric1_speedy2_ddi_sclk",
2640 GATE(CLK_GOUT_PERIC1_SPEEDY2_TSP1_CLK, "gout_peric1_speedy2_tsp1_clk",
2644 GATE(CLK_GOUT_PERIC1_SPEEDY2_TSP2_CLK, "gout_peric1_speedy2_tsp2_clk",
2648 GATE(CLK_GOUT_PERIC1_SPI_CAM0_PCLK, "gout_peric1_spi_cam0_pclk",
2652 GATE(CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK,
2656 GATE(CLK_GOUT_PERIC1_SPI_CAM1_PCLK, "gout_peric1_spi_cam1_pclk",
2660 GATE(CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK,
2664 GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
2668 GATE(CLK_GOUT_PERIC1_UART_BT_EXT_UCLK, "gout_peric1_uart_bt_ext_uclk",
2672 GATE(CLK_GOUT_PERIC1_UART_BT_PCLK, "gout_peric1_uart_bt_pclk",
2675 GATE(CLK_GOUT_PERIC1_USI04_I_PCLK, "gout_peric1_usi04_i_pclk",
2678 GATE(CLK_GOUT_PERIC1_USI04_I_SCLK_USI, "gout_peric1_usi04_i_sclk_usi",
2682 GATE(CLK_GOUT_PERIC1_USI05_I_PCLK, "gout_peric1_usi05_i_pclk",
2685 GATE(CLK_GOUT_PERIC1_USI05_I_SCLK_USI, "gout_peric1_usi05_i_sclk_usi",
2689 GATE(CLK_GOUT_PERIC1_USI06_I_PCLK, "gout_peric1_usi06_i_pclk",
2692 GATE(CLK_GOUT_PERIC1_USI06_I_SCLK_USI, "gout_peric1_usi06_i_sclk_usi",
2696 GATE(CLK_GOUT_PERIC1_USI07_I_PCLK, "gout_peric1_usi07_i_pclk",
2699 GATE(CLK_GOUT_PERIC1_USI07_I_SCLK_USI, "gout_peric1_usi07_i_sclk_usi",
2703 GATE(CLK_GOUT_PERIC1_USI08_I_PCLK, "gout_peric1_usi08_i_pclk",
2706 GATE(CLK_GOUT_PERIC1_USI08_I_SCLK_USI, "gout_peric1_usi08_i_sclk_usi",
2710 GATE(CLK_GOUT_PERIC1_USI09_I_PCLK, "gout_peric1_usi09_i_pclk",
2713 GATE(CLK_GOUT_PERIC1_USI09_I_SCLK_USI, "gout_peric1_usi09_i_sclk_usi",
2717 GATE(CLK_GOUT_PERIC1_USI10_I_PCLK, "gout_peric1_usi10_i_pclk",
2720 GATE(CLK_GOUT_PERIC1_USI10_I_SCLK_USI, "gout_peric1_usi10_i_sclk_usi",
2724 GATE(CLK_GOUT_PERIC1_USI11_I_PCLK, "gout_peric1_usi11_i_pclk",
2727 GATE(CLK_GOUT_PERIC1_USI11_I_SCLK_USI, "gout_peric1_usi11_i_sclk_usi",
2731 GATE(CLK_GOUT_PERIC1_USI12_I_PCLK, "gout_peric1_usi12_i_pclk",
2734 GATE(CLK_GOUT_PERIC1_USI12_I_SCLK_USI, "gout_peric1_usi12_i_sclk_usi",
2738 GATE(CLK_GOUT_PERIC1_USI13_I_PCLK, "gout_peric1_usi13_i_pclk",
2741 GATE(CLK_GOUT_PERIC1_USI13_I_SCLK_USI, "gout_peric1_usi13_i_sclk_usi",
2745 GATE(CLK_GOUT_PERIC1_XIU_P_PERIC1_ACLK,