Lines Matching +full:bank +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
15 #include "clk-rcg.h"
20 ns >>= s->src_sel_shift; in ns_to_src()
30 mask <<= s->src_sel_shift; in src_to_ns()
33 ns |= src << s->src_sel_shift; in src_to_ns()
44 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_get_parent()
47 ns = ns_to_src(&rcg->s, ns); in clk_rcg_get_parent()
49 if (ns == rcg->s.parent_map[i].cfg) in clk_rcg_get_parent()
58 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) in reg_to_bank() argument
60 bank &= BIT(rcg->mux_sel_bit); in reg_to_bank()
61 return !!bank; in reg_to_bank()
69 int bank; in clk_dyn_rcg_get_parent() local
73 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in clk_dyn_rcg_get_parent()
76 bank = reg_to_bank(rcg, reg); in clk_dyn_rcg_get_parent()
77 s = &rcg->s[bank]; in clk_dyn_rcg_get_parent()
79 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); in clk_dyn_rcg_get_parent()
85 if (ns == s->parent_map[i].cfg) in clk_dyn_rcg_get_parent()
99 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_set_parent()
100 ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns); in clk_rcg_set_parent()
101 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); in clk_rcg_set_parent()
108 md >>= mn->m_val_shift; in md_to_m()
109 md &= BIT(mn->width) - 1; in md_to_m()
115 ns >>= p->pre_div_shift; in ns_to_pre_div()
116 ns &= BIT(p->pre_div_width) - 1; in ns_to_pre_div()
124 mask = BIT(p->pre_div_width) - 1; in pre_div_to_ns()
125 mask <<= p->pre_div_shift; in pre_div_to_ns()
128 ns |= pre_div << p->pre_div_shift; in pre_div_to_ns()
136 mask_w = BIT(mn->width) - 1; in mn_to_md()
137 mask = (mask_w << mn->m_val_shift) | mask_w; in mn_to_md()
141 m <<= mn->m_val_shift; in mn_to_md()
151 ns = ~ns >> mn->n_val_shift; in ns_m_to_n()
152 ns &= BIT(mn->width) - 1; in ns_m_to_n()
158 val >>= mn->mnctr_mode_shift; in reg_to_mnctr_mode()
167 mask = BIT(mn->width) - 1; in mn_to_ns()
168 mask <<= mn->n_val_shift; in mn_to_ns()
172 n = n - m; in mn_to_ns()
174 n &= BIT(mn->width) - 1; in mn_to_ns()
175 n <<= mn->n_val_shift; in mn_to_ns()
186 mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift; in mn_to_reg()
187 mask |= BIT(mn->mnctr_en_bit); in mn_to_reg()
191 val |= BIT(mn->mnctr_en_bit); in mn_to_reg()
192 val |= MNCTR_MODE_DUAL << mn->mnctr_mode_shift; in mn_to_reg()
201 int bank, new_bank, ret, index; in configure_bank() local
207 bool banked_mn = !!rcg->mn[1].width; in configure_bank()
208 bool banked_p = !!rcg->p[1].pre_div_width; in configure_bank()
209 struct clk_hw *hw = &rcg->clkr.hw; in configure_bank()
211 enabled = __clk_is_enabled(hw->clk); in configure_bank()
213 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in configure_bank()
216 bank = reg_to_bank(rcg, reg); in configure_bank()
217 new_bank = enabled ? !bank : bank; in configure_bank()
219 ns_reg = rcg->ns_reg[new_bank]; in configure_bank()
220 ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns); in configure_bank()
225 mn = &rcg->mn[new_bank]; in configure_bank()
226 md_reg = rcg->md_reg[new_bank]; in configure_bank()
228 ns |= BIT(mn->mnctr_reset_bit); in configure_bank()
229 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); in configure_bank()
233 ret = regmap_read(rcg->clkr.regmap, md_reg, &md); in configure_bank()
236 md = mn_to_md(mn, f->m, f->n, md); in configure_bank()
237 ret = regmap_write(rcg->clkr.regmap, md_reg, md); in configure_bank()
240 ns = mn_to_ns(mn, f->m, f->n, ns); in configure_bank()
241 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); in configure_bank()
246 if (rcg->ns_reg[0] != rcg->ns_reg[1]) { in configure_bank()
247 ns = mn_to_reg(mn, f->m, f->n, ns); in configure_bank()
248 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); in configure_bank()
252 reg = mn_to_reg(mn, f->m, f->n, reg); in configure_bank()
253 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, in configure_bank()
259 ns &= ~BIT(mn->mnctr_reset_bit); in configure_bank()
260 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); in configure_bank()
266 p = &rcg->p[new_bank]; in configure_bank()
267 ns = pre_div_to_ns(p, f->pre_div - 1, ns); in configure_bank()
270 s = &rcg->s[new_bank]; in configure_bank()
271 index = qcom_find_src_index(hw, s->parent_map, f->src); in configure_bank()
274 ns = src_to_ns(s, s->parent_map[index].cfg, ns); in configure_bank()
275 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); in configure_bank()
280 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in configure_bank()
283 reg ^= BIT(rcg->mux_sel_bit); in configure_bank()
284 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg); in configure_bank()
295 int bank; in clk_dyn_rcg_set_parent() local
297 bool banked_mn = !!rcg->mn[1].width; in clk_dyn_rcg_set_parent()
298 bool banked_p = !!rcg->p[1].pre_div_width; in clk_dyn_rcg_set_parent()
300 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in clk_dyn_rcg_set_parent()
301 bank = reg_to_bank(rcg, reg); in clk_dyn_rcg_set_parent()
303 regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); in clk_dyn_rcg_set_parent()
306 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md); in clk_dyn_rcg_set_parent()
307 f.m = md_to_m(&rcg->mn[bank], md); in clk_dyn_rcg_set_parent()
308 f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m); in clk_dyn_rcg_set_parent()
312 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1; in clk_dyn_rcg_set_parent()
314 f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index); in clk_dyn_rcg_set_parent()
322 * rate = ----------- x ---
346 struct mn *mn = &rcg->mn; in clk_rcg_recalc_rate()
348 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_recalc_rate()
349 pre_div = ns_to_pre_div(&rcg->p, ns); in clk_rcg_recalc_rate()
351 if (rcg->mn.width) { in clk_rcg_recalc_rate()
352 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md); in clk_rcg_recalc_rate()
356 if (rcg->clkr.enable_reg != rcg->ns_reg) in clk_rcg_recalc_rate()
357 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode); in clk_rcg_recalc_rate()
371 int bank; in clk_dyn_rcg_recalc_rate() local
373 bool banked_p = !!rcg->p[1].pre_div_width; in clk_dyn_rcg_recalc_rate()
374 bool banked_mn = !!rcg->mn[1].width; in clk_dyn_rcg_recalc_rate()
376 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in clk_dyn_rcg_recalc_rate()
377 bank = reg_to_bank(rcg, reg); in clk_dyn_rcg_recalc_rate()
379 regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); in clk_dyn_rcg_recalc_rate()
383 mn = &rcg->mn[bank]; in clk_dyn_rcg_recalc_rate()
384 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md); in clk_dyn_rcg_recalc_rate()
388 if (rcg->ns_reg[0] != rcg->ns_reg[1]) in clk_dyn_rcg_recalc_rate()
394 pre_div = ns_to_pre_div(&rcg->p[bank], ns); in clk_dyn_rcg_recalc_rate()
403 unsigned long clk_flags, rate = req->rate; in _freq_tbl_determine_rate()
409 return -EINVAL; in _freq_tbl_determine_rate()
411 index = qcom_find_src_index(hw, parent_map, f->src); in _freq_tbl_determine_rate()
418 rate = rate * f->pre_div; in _freq_tbl_determine_rate()
419 if (f->n) { in _freq_tbl_determine_rate()
421 tmp = tmp * f->n; in _freq_tbl_determine_rate()
422 do_div(tmp, f->m); in _freq_tbl_determine_rate()
428 req->best_parent_hw = p; in _freq_tbl_determine_rate()
429 req->best_parent_rate = rate; in _freq_tbl_determine_rate()
430 req->rate = f->freq; in _freq_tbl_determine_rate()
440 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, in clk_rcg_determine_rate()
441 rcg->s.parent_map); in clk_rcg_determine_rate()
449 int bank; in clk_dyn_rcg_determine_rate() local
452 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in clk_dyn_rcg_determine_rate()
453 bank = reg_to_bank(rcg, reg); in clk_dyn_rcg_determine_rate()
454 s = &rcg->s[bank]; in clk_dyn_rcg_determine_rate()
456 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, s->parent_map); in clk_dyn_rcg_determine_rate()
463 const struct freq_tbl *f = rcg->freq_tbl; in clk_rcg_bypass_determine_rate()
465 int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src); in clk_rcg_bypass_determine_rate()
467 req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index); in clk_rcg_bypass_determine_rate()
468 req->best_parent_rate = clk_hw_round_rate(p, req->rate); in clk_rcg_bypass_determine_rate()
469 req->rate = req->best_parent_rate; in clk_rcg_bypass_determine_rate()
477 struct mn *mn = &rcg->mn; in __clk_rcg_set_rate()
481 if (rcg->mn.reset_in_cc) in __clk_rcg_set_rate()
482 reset_reg = rcg->clkr.enable_reg; in __clk_rcg_set_rate()
484 reset_reg = rcg->ns_reg; in __clk_rcg_set_rate()
486 if (rcg->mn.width) { in __clk_rcg_set_rate()
487 mask = BIT(mn->mnctr_reset_bit); in __clk_rcg_set_rate()
488 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask); in __clk_rcg_set_rate()
490 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md); in __clk_rcg_set_rate()
491 md = mn_to_md(mn, f->m, f->n, md); in __clk_rcg_set_rate()
492 regmap_write(rcg->clkr.regmap, rcg->md_reg, md); in __clk_rcg_set_rate()
494 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in __clk_rcg_set_rate()
496 if (rcg->clkr.enable_reg != rcg->ns_reg) { in __clk_rcg_set_rate()
497 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl); in __clk_rcg_set_rate()
498 ctl = mn_to_reg(mn, f->m, f->n, ctl); in __clk_rcg_set_rate()
499 regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl); in __clk_rcg_set_rate()
501 ns = mn_to_reg(mn, f->m, f->n, ns); in __clk_rcg_set_rate()
503 ns = mn_to_ns(mn, f->m, f->n, ns); in __clk_rcg_set_rate()
505 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in __clk_rcg_set_rate()
508 ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns); in __clk_rcg_set_rate()
509 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); in __clk_rcg_set_rate()
511 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0); in __clk_rcg_set_rate()
522 f = qcom_find_freq(rcg->freq_tbl, rate); in clk_rcg_set_rate()
524 return -EINVAL; in clk_rcg_set_rate()
535 f = qcom_find_freq_floor(rcg->freq_tbl, rate); in clk_rcg_set_floor_rate()
537 return -EINVAL; in clk_rcg_set_floor_rate()
547 return __clk_rcg_set_rate(rcg, rcg->freq_tbl); in clk_rcg_bypass_set_rate()
555 p = req->best_parent_hw; in clk_rcg_bypass2_determine_rate()
556 req->best_parent_rate = clk_hw_round_rate(p, req->rate); in clk_rcg_bypass2_determine_rate()
557 req->rate = req->best_parent_rate; in clk_rcg_bypass2_determine_rate()
570 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_bypass2_set_rate()
574 src = ns_to_src(&rcg->s, ns); in clk_rcg_bypass2_set_rate()
575 f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1; in clk_rcg_bypass2_set_rate()
578 if (src == rcg->s.parent_map[i].cfg) { in clk_rcg_bypass2_set_rate()
579 f.src = rcg->s.parent_map[i].src; in clk_rcg_bypass2_set_rate()
584 return -EINVAL; in clk_rcg_bypass2_set_rate()
614 for (; frac->num; frac++) { in clk_rcg_pixel_determine_rate()
615 request = (req->rate * frac->den) / frac->num; in clk_rcg_pixel_determine_rate()
617 src_rate = clk_hw_round_rate(req->best_parent_hw, request); in clk_rcg_pixel_determine_rate()
619 if ((src_rate < (request - delta)) || in clk_rcg_pixel_determine_rate()
623 req->best_parent_rate = src_rate; in clk_rcg_pixel_determine_rate()
624 req->rate = (src_rate * frac->num) / frac->den; in clk_rcg_pixel_determine_rate()
628 return -EINVAL; in clk_rcg_pixel_determine_rate()
642 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_pixel_set_rate()
646 src = ns_to_src(&rcg->s, ns); in clk_rcg_pixel_set_rate()
649 if (src == rcg->s.parent_map[i].cfg) { in clk_rcg_pixel_set_rate()
650 f.src = rcg->s.parent_map[i].src; in clk_rcg_pixel_set_rate()
659 for (; frac->num; frac++) { in clk_rcg_pixel_set_rate()
660 request = (rate * frac->den) / frac->num; in clk_rcg_pixel_set_rate()
662 if ((parent_rate < (request - delta)) || in clk_rcg_pixel_set_rate()
666 f.m = frac->num; in clk_rcg_pixel_set_rate()
667 f.n = frac->den; in clk_rcg_pixel_set_rate()
672 return -EINVAL; in clk_rcg_pixel_set_rate()
685 int pre_div_max = BIT(rcg->p.pre_div_width); in clk_rcg_esc_determine_rate()
689 if (req->rate == 0) in clk_rcg_esc_determine_rate()
690 return -EINVAL; in clk_rcg_esc_determine_rate()
692 src_rate = clk_hw_get_rate(req->best_parent_hw); in clk_rcg_esc_determine_rate()
694 div = src_rate / req->rate; in clk_rcg_esc_determine_rate()
697 req->best_parent_rate = src_rate; in clk_rcg_esc_determine_rate()
698 req->rate = src_rate / div; in clk_rcg_esc_determine_rate()
702 return -EINVAL; in clk_rcg_esc_determine_rate()
710 int pre_div_max = BIT(rcg->p.pre_div_width); in clk_rcg_esc_set_rate()
716 return -EINVAL; in clk_rcg_esc_set_rate()
718 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_esc_set_rate()
722 ns = ns_to_src(&rcg->s, ns); in clk_rcg_esc_set_rate()
725 if (ns == rcg->s.parent_map[i].cfg) { in clk_rcg_esc_set_rate()
726 f.src = rcg->s.parent_map[i].src; in clk_rcg_esc_set_rate()
738 return -EINVAL; in clk_rcg_esc_set_rate()
748 * This type of clock has a glitch-free mux that switches between the output of
766 f = qcom_find_freq(rcg->freq_tbl, rate); in clk_rcg_lcc_set_rate()
768 return -EINVAL; in clk_rcg_lcc_set_rate()
771 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0); in clk_rcg_lcc_set_rate()
774 if (__clk_is_enabled(hw->clk)) in clk_rcg_lcc_set_rate()
775 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm); in clk_rcg_lcc_set_rate()
786 return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm); in clk_rcg_lcc_enable()
795 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0); in clk_rcg_lcc_disable()
803 f = qcom_find_freq(rcg->freq_tbl, rate); in __clk_dyn_rcg_set_rate()
805 return -EINVAL; in __clk_dyn_rcg_set_rate()