Lines Matching full:aclk

301  * The first 2 SRAM banks depend on ACLK/CPU clock which is by default PLL0
326  * @aclk: ACLK clock
333 	struct clk_hw			aclk;  member
337 #define to_k210_sysclk(_hw)	container_of(_hw, struct k210_sysclk, aclk)
340  * Set ACLK parent selector: 0 for IN0, 1 for PLL0.
398 	 * For PLL0, we need to re-parent ACLK to IN0 to keep the CPU cores and  in k210_pll_enable_hw()
645  * ACLK has IN0 and PLL0 as parents.
657 	init.name = "aclk";  in k210_register_aclk()
661 	ksc->aclk.init = &init;  in k210_register_aclk()
663 	ret = of_clk_hw_register(np, &ksc->aclk);  in k210_register_aclk()
665 		pr_err("%pOFP: register aclk failed\n", np);  in k210_register_aclk()
861 		.hw = &ksc->aclk,  in k210_register_aclk_child()
931 	/* Clocks with aclk as source */  in k210_clk_init()
1004 	/* Make sure ACLK selector is set to PLL0 */  in k210_clk_early_init()