Lines Matching full:7
20 #define PCMCIA_ATTR16 7
25 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
28 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
31 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
34 /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
37 /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
49 /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
58 /* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
61 /* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
64 /* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
67 /* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
70 /* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
73 /* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
79 /* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
87 /* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
89 /* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */
91 /* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */
93 /* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */
95 /* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */
100 (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5)