Lines Matching +full:compound +full:- +full:device
1 // SPDX-License-Identifier: GPL-2.0-or-later
33 #include <asm/ppc-pci.h>
34 #include <asm/pnv-pci.h>
40 static int eeh_event_irq = -EINVAL;
44 dev_dbg(&pdev->dev, "EEH: Setting up device\n"); in pnv_pcibios_bus_add_device()
69 struct pci_controller *hose = filp->private_data; in pnv_eeh_ei_write()
76 if (!eeh_ops || !eeh_ops->err_inject) in pnv_eeh_ei_write()
77 return -ENXIO; in pnv_eeh_ei_write()
82 return -EFAULT; in pnv_eeh_ei_write()
88 return -EINVAL; in pnv_eeh_ei_write()
93 return -ENODEV; in pnv_eeh_ei_write()
96 ret = eeh_ops->err_inject(pe, type, func, addr, mask); in pnv_eeh_ei_write()
108 struct pnv_phb *phb = hose->private_data; in pnv_eeh_dbgfs_set()
110 out_be64(phb->regs + offset, val); in pnv_eeh_dbgfs_set()
117 struct pnv_phb *phb = hose->private_data; in pnv_eeh_dbgfs_get()
119 *val = in_be64(phb->regs + offset); in pnv_eeh_dbgfs_get()
151 phb = hose->private_data; in pnv_eeh_enable_phbs()
158 phb->flags |= PNV_PHB_FLAG_EEH; in pnv_eeh_enable_phbs()
160 phb->flags &= ~PNV_PHB_FLAG_EEH; in pnv_eeh_enable_phbs()
165 * pnv_eeh_post_init - EEH platform dependent post initialization
189 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); in pnv_eeh_post_init()
203 phb = hose->private_data; in pnv_eeh_post_init()
207 if (phb->has_dbgfs || !phb->dbgfs) in pnv_eeh_post_init()
210 phb->has_dbgfs = 1; in pnv_eeh_post_init()
212 phb->dbgfs, hose, in pnv_eeh_post_init()
216 phb->dbgfs, hose, in pnv_eeh_post_init()
219 phb->dbgfs, hose, in pnv_eeh_post_init()
222 phb->dbgfs, hose, in pnv_eeh_post_init()
239 /* Check if the device supports capabilities */ in pnv_eeh_find_cap()
244 while (cnt--) { in pnv_eeh_find_cap()
269 int pos = 256, ttl = (4096 - 256) / 8; in pnv_eeh_find_ecap()
271 if (!edev || !edev->pcie_cap) in pnv_eeh_find_ecap()
278 while (ttl-- > 0) { in pnv_eeh_find_ecap()
295 struct pci_controller *hose = pdev->bus->sysdata; in pnv_eeh_get_upstream_pe()
296 struct pnv_phb *phb = hose->private_data; in pnv_eeh_get_upstream_pe()
297 struct pci_dev *parent = pdev->bus->self; in pnv_eeh_get_upstream_pe()
301 if (pdev->is_virtfn) in pnv_eeh_get_upstream_pe()
302 parent = pdev->physfn; in pnv_eeh_get_upstream_pe()
309 return eeh_pe_get(phb->hose, ioda_pe->pe_number); in pnv_eeh_get_upstream_pe()
316 * pnv_eeh_probe - Do probe on PCI device
324 struct pci_controller *hose = pdn->phb; in pnv_eeh_probe()
325 struct pnv_phb *phb = hose->private_data; in pnv_eeh_probe()
330 int config_addr = (pdn->busno << 8) | (pdn->devfn); in pnv_eeh_probe()
338 if (!edev || edev->pe) in pnv_eeh_probe()
342 if (edev->pdev) { in pnv_eeh_probe()
344 __func__, hose->global_number, config_addr >> 8, in pnv_eeh_probe()
349 /* Skip for PCI-ISA bridge */ in pnv_eeh_probe()
350 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) in pnv_eeh_probe()
353 eeh_edev_dbg(edev, "Probing device\n"); in pnv_eeh_probe()
355 /* Initialize eeh device */ in pnv_eeh_probe()
356 edev->mode &= 0xFFFFFF00; in pnv_eeh_probe()
357 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); in pnv_eeh_probe()
358 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); in pnv_eeh_probe()
359 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); in pnv_eeh_probe()
360 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); in pnv_eeh_probe()
361 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { in pnv_eeh_probe()
362 edev->mode |= EEH_DEV_BRIDGE; in pnv_eeh_probe()
363 if (edev->pcie_cap) { in pnv_eeh_probe()
364 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, in pnv_eeh_probe()
368 edev->mode |= EEH_DEV_ROOT_PORT; in pnv_eeh_probe()
370 edev->mode |= EEH_DEV_DS_PORT; in pnv_eeh_probe()
374 edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; in pnv_eeh_probe()
381 eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n", ret); in pnv_eeh_probe()
398 * Broadcom BCM5718 2-ports NICs (14e4:1656) in pnv_eeh_probe()
399 * Broadcom Austin 4-ports NICs (14e4:1657) in pnv_eeh_probe()
400 * Broadcom Shiner 4-ports 1G NICs (14e4:168a) in pnv_eeh_probe()
401 * Broadcom Shiner 2-ports 10G NICs (14e4:168e) in pnv_eeh_probe()
403 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && in pnv_eeh_probe()
404 pdn->device_id == 0x1656) || in pnv_eeh_probe()
405 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && in pnv_eeh_probe()
406 pdn->device_id == 0x1657) || in pnv_eeh_probe()
407 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && in pnv_eeh_probe()
408 pdn->device_id == 0x168a) || in pnv_eeh_probe()
409 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && in pnv_eeh_probe()
410 pdn->device_id == 0x168e)) in pnv_eeh_probe()
411 edev->pe->state |= EEH_PE_CFG_RESTRICTED; in pnv_eeh_probe()
419 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { in pnv_eeh_probe()
420 edev->pe->bus = pci_find_bus(hose->global_number, in pnv_eeh_probe()
421 pdn->busno); in pnv_eeh_probe()
422 if (edev->pe->bus) in pnv_eeh_probe()
423 edev->pe->state |= EEH_PE_PRI_BUS; in pnv_eeh_probe()
439 eeh_edev_dbg(edev, "EEH enabled on device\n"); in pnv_eeh_probe()
445 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
455 struct pci_controller *hose = pe->phb; in pnv_eeh_set_option()
456 struct pnv_phb *phb = hose->private_data; in pnv_eeh_set_option()
463 return -EPERM; in pnv_eeh_set_option()
478 return -EINVAL; in pnv_eeh_set_option()
481 /* Freeze master and slave PEs if PHB supports compound PEs */ in pnv_eeh_set_option()
483 if (phb->freeze_pe) { in pnv_eeh_set_option()
484 phb->freeze_pe(phb, pe->addr); in pnv_eeh_set_option()
488 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); in pnv_eeh_set_option()
490 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", in pnv_eeh_set_option()
491 __func__, rc, phb->hose->global_number, in pnv_eeh_set_option()
492 pe->addr); in pnv_eeh_set_option()
493 return -EIO; in pnv_eeh_set_option()
500 if (phb->unfreeze_pe) in pnv_eeh_set_option()
501 return phb->unfreeze_pe(phb, pe->addr, opt); in pnv_eeh_set_option()
503 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); in pnv_eeh_set_option()
505 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", in pnv_eeh_set_option()
506 __func__, rc, option, phb->hose->global_number, in pnv_eeh_set_option()
507 pe->addr); in pnv_eeh_set_option()
508 return -EIO; in pnv_eeh_set_option()
516 struct pnv_phb *phb = pe->phb->private_data; in pnv_eeh_get_phb_diag()
519 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, in pnv_eeh_get_phb_diag()
520 phb->diag_data_size); in pnv_eeh_get_phb_diag()
522 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", in pnv_eeh_get_phb_diag()
523 __func__, rc, pe->phb->global_number); in pnv_eeh_get_phb_diag()
528 struct pnv_phb *phb = pe->phb->private_data; in pnv_eeh_get_phb_state()
534 rc = opal_pci_eeh_freeze_status(phb->opal_id, in pnv_eeh_get_phb_state()
535 pe->addr, in pnv_eeh_get_phb_state()
541 __func__, rc, phb->hose->global_number); in pnv_eeh_get_phb_state()
547 * first time, to dump the PHB diag-data. in pnv_eeh_get_phb_state()
554 } else if (!(pe->state & EEH_PE_ISOLATED)) { in pnv_eeh_get_phb_state()
559 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); in pnv_eeh_get_phb_state()
567 struct pnv_phb *phb = pe->phb->private_data; in pnv_eeh_get_pe_state()
579 if (pe->state & EEH_PE_RESET) { in pnv_eeh_get_pe_state()
589 * supports compound PE, let it handle that. in pnv_eeh_get_pe_state()
591 if (phb->get_pe_state) { in pnv_eeh_get_pe_state()
592 fstate = phb->get_pe_state(phb, pe->addr); in pnv_eeh_get_pe_state()
594 rc = opal_pci_eeh_freeze_status(phb->opal_id, in pnv_eeh_get_pe_state()
595 pe->addr, in pnv_eeh_get_pe_state()
600 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", in pnv_eeh_get_pe_state()
601 __func__, rc, phb->hose->global_number, in pnv_eeh_get_pe_state()
602 pe->addr); in pnv_eeh_get_pe_state()
637 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", in pnv_eeh_get_pe_state()
638 __func__, phb->hose->global_number, in pnv_eeh_get_pe_state()
639 pe->addr, fstate); in pnv_eeh_get_pe_state()
643 * If PHB supports compound PE, to freeze all in pnv_eeh_get_pe_state()
647 * first time, to dump the PHB diag-data. in pnv_eeh_get_pe_state()
653 !(pe->state & EEH_PE_ISOLATED)) { in pnv_eeh_get_pe_state()
654 if (phb->freeze_pe) in pnv_eeh_get_pe_state()
655 phb->freeze_pe(phb, pe->addr); in pnv_eeh_get_pe_state()
661 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); in pnv_eeh_get_pe_state()
668 * pnv_eeh_get_state - Retrieve PE state
672 * Retrieve the state of the specified PE. For IODA-compitable
681 if (pe->type & EEH_PE_PHB) in pnv_eeh_get_state()
721 struct pnv_phb *phb = hose->private_data; in pnv_eeh_phb_reset()
725 __func__, hose->global_number, option); in pnv_eeh_phb_reset()
730 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_phb_reset()
734 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_phb_reset()
747 rc = pnv_eeh_poll(phb->opal_id); in pnv_eeh_phb_reset()
756 return -EIO; in pnv_eeh_phb_reset()
763 struct pnv_phb *phb = hose->private_data; in pnv_eeh_root_reset()
767 __func__, hose->global_number, option); in pnv_eeh_root_reset()
775 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_root_reset()
779 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_root_reset()
783 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_root_reset()
791 rc = pnv_eeh_poll(phb->opal_id); in pnv_eeh_root_reset()
796 return -EIO; in pnv_eeh_root_reset()
803 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); in __pnv_eeh_bridge_reset()
805 int aer = edev ? edev->aer_cap : 0; in __pnv_eeh_bridge_reset()
809 __func__, pci_domain_nr(dev->bus), in __pnv_eeh_bridge_reset()
810 dev->bus->number, option); in __pnv_eeh_bridge_reset()
817 eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK, in __pnv_eeh_bridge_reset()
820 eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK, in __pnv_eeh_bridge_reset()
824 eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl); in __pnv_eeh_bridge_reset()
826 eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl); in __pnv_eeh_bridge_reset()
831 eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl); in __pnv_eeh_bridge_reset()
833 eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl); in __pnv_eeh_bridge_reset()
839 eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK, in __pnv_eeh_bridge_reset()
842 eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK, in __pnv_eeh_bridge_reset()
854 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pnv_eeh_bridge_reset()
855 struct pnv_phb *phb = hose->private_data; in pnv_eeh_bridge_reset()
857 uint64_t id = PCI_SLOT_ID(phb->opal_id, pci_dev_id(pdev)); in pnv_eeh_bridge_reset()
862 if (!dn || !of_property_present(dn, "ibm,reset-by-firmware")) in pnv_eeh_bridge_reset()
866 __func__, pci_domain_nr(pdev->bus), in pnv_eeh_bridge_reset()
867 pdev->bus->number, option); in pnv_eeh_bridge_reset()
879 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", in pnv_eeh_bridge_reset()
881 return -EINVAL; in pnv_eeh_bridge_reset()
890 return (rc == OPAL_SUCCESS) ? 0 : -EIO; in pnv_eeh_bridge_reset()
897 if (pci_is_root_bus(dev->bus)) { in pnv_pci_reset_secondary_bus()
898 hose = pci_bus_to_host(dev->bus); in pnv_pci_reset_secondary_bus()
910 struct eeh_dev *edev = pdn->edev; in pnv_eeh_wait_for_pending()
915 eeh_ops->read_config(edev, pos, 2, &status); in pnv_eeh_wait_for_pending()
924 pdn->phb->global_number, pdn->busno, in pnv_eeh_wait_for_pending()
925 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); in pnv_eeh_wait_for_pending()
933 if (WARN_ON(!edev->pcie_cap)) in pnv_eeh_do_flr()
934 return -ENOTTY; in pnv_eeh_do_flr()
936 eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); in pnv_eeh_do_flr()
938 return -ENOTTY; in pnv_eeh_do_flr()
944 edev->pcie_cap + PCI_EXP_DEVSTA, in pnv_eeh_do_flr()
946 eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, in pnv_eeh_do_flr()
949 eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, in pnv_eeh_do_flr()
954 eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, in pnv_eeh_do_flr()
957 eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, in pnv_eeh_do_flr()
971 if (WARN_ON(!edev->af_cap)) in pnv_eeh_do_af_flr()
972 return -ENOTTY; in pnv_eeh_do_af_flr()
974 eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap); in pnv_eeh_do_af_flr()
976 return -ENOTTY; in pnv_eeh_do_af_flr()
982 * Wait for Transaction Pending bit to clear. A word-aligned in pnv_eeh_do_af_flr()
987 edev->af_cap + PCI_AF_CTRL, in pnv_eeh_do_af_flr()
989 eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, in pnv_eeh_do_af_flr()
994 eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0); in pnv_eeh_do_af_flr()
1008 /* The VF PE should have only one child device */ in pnv_eeh_reset_vf_pe()
1009 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); in pnv_eeh_reset_vf_pe()
1012 return -ENXIO; in pnv_eeh_reset_vf_pe()
1022 * pnv_eeh_reset - Reset the specified PE
1029 * PCI device sensitive PE, we will try to reset the device
1035 struct pci_controller *hose = pe->phb; in pnv_eeh_reset()
1054 if (pe->type & EEH_PE_PHB) in pnv_eeh_reset()
1064 phb = hose->private_data; in pnv_eeh_reset()
1065 if (phb->model == PNV_PHB_MODEL_P7IOC && in pnv_eeh_reset()
1068 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_reset()
1074 return -EIO; in pnv_eeh_reset()
1078 if (pe->type & EEH_PE_VF) in pnv_eeh_reset()
1083 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", in pnv_eeh_reset()
1084 __func__, pe->phb->global_number, pe->addr); in pnv_eeh_reset()
1085 return -EIO; in pnv_eeh_reset()
1104 * NB: Skiboot and pnv_eeh_bridge_reset() also no-op the in pnv_eeh_reset()
1105 * de-assert step. It's like the OPAL reset API was in pnv_eeh_reset()
1111 rc = pci_bus_error_reset(bus->self); in pnv_eeh_reset()
1117 if (pci_is_root_bus(bus->parent)) in pnv_eeh_reset()
1119 return pnv_eeh_bridge_reset(bus->self, option); in pnv_eeh_reset()
1123 * pnv_eeh_get_log - Retrieve error log
1135 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); in pnv_eeh_get_log()
1141 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1154 * pnv_pe_err_inject - Inject specified error to the indicated PE
1168 struct pci_controller *hose = pe->phb; in pnv_eeh_err_inject()
1169 struct pnv_phb *phb = hose->private_data; in pnv_eeh_err_inject()
1176 return -ERANGE; in pnv_eeh_err_inject()
1183 return -ERANGE; in pnv_eeh_err_inject()
1190 return -ENXIO; in pnv_eeh_err_inject()
1194 rc = opal_pci_err_inject(phb->opal_id, pe->addr, in pnv_eeh_err_inject()
1198 "%d-%d to PHB#%x-PE#%x\n", in pnv_eeh_err_inject()
1200 hose->global_number, pe->addr); in pnv_eeh_err_inject()
1201 return -EIO; in pnv_eeh_err_inject()
1211 if (!edev || !edev->pe) in pnv_eeh_cfg_blocked()
1219 if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) in pnv_eeh_cfg_blocked()
1222 if (edev->pe->state & EEH_PE_CFG_BLOCKED) in pnv_eeh_cfg_blocked()
1261 if (data->gemXfir || data->gemRfir || in pnv_eeh_dump_hub_diag_common()
1262 data->gemRirqfir || data->gemMask || data->gemRwof) in pnv_eeh_dump_hub_diag_common()
1264 be64_to_cpu(data->gemXfir), in pnv_eeh_dump_hub_diag_common()
1265 be64_to_cpu(data->gemRfir), in pnv_eeh_dump_hub_diag_common()
1266 be64_to_cpu(data->gemRirqfir), in pnv_eeh_dump_hub_diag_common()
1267 be64_to_cpu(data->gemMask), in pnv_eeh_dump_hub_diag_common()
1268 be64_to_cpu(data->gemRwof)); in pnv_eeh_dump_hub_diag_common()
1271 if (data->lemFir || data->lemErrMask || in pnv_eeh_dump_hub_diag_common()
1272 data->lemAction0 || data->lemAction1 || data->lemWof) in pnv_eeh_dump_hub_diag_common()
1274 be64_to_cpu(data->lemFir), in pnv_eeh_dump_hub_diag_common()
1275 be64_to_cpu(data->lemErrMask), in pnv_eeh_dump_hub_diag_common()
1276 be64_to_cpu(data->lemAction0), in pnv_eeh_dump_hub_diag_common()
1277 be64_to_cpu(data->lemAction1), in pnv_eeh_dump_hub_diag_common()
1278 be64_to_cpu(data->lemWof)); in pnv_eeh_dump_hub_diag_common()
1283 struct pnv_phb *phb = hose->private_data; in pnv_eeh_get_and_dump_hub_diag()
1285 (struct OpalIoP7IOCErrorData*)phb->diag_data; in pnv_eeh_get_and_dump_hub_diag()
1288 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); in pnv_eeh_get_and_dump_hub_diag()
1290 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", in pnv_eeh_get_and_dump_hub_diag()
1291 __func__, phb->hub_id, rc); in pnv_eeh_get_and_dump_hub_diag()
1295 switch (be16_to_cpu(data->type)) { in pnv_eeh_get_and_dump_hub_diag()
1297 pr_info("P7IOC diag-data for RGC\n\n"); in pnv_eeh_get_and_dump_hub_diag()
1299 if (data->rgc.rgcStatus || data->rgc.rgcLdcp) in pnv_eeh_get_and_dump_hub_diag()
1301 be64_to_cpu(data->rgc.rgcStatus), in pnv_eeh_get_and_dump_hub_diag()
1302 be64_to_cpu(data->rgc.rgcLdcp)); in pnv_eeh_get_and_dump_hub_diag()
1305 pr_info("P7IOC diag-data for BI %s\n\n", in pnv_eeh_get_and_dump_hub_diag()
1306 data->bi.biDownbound ? "Downbound" : "Upbound"); in pnv_eeh_get_and_dump_hub_diag()
1308 if (data->bi.biLdcp0 || data->bi.biLdcp1 || in pnv_eeh_get_and_dump_hub_diag()
1309 data->bi.biLdcp2 || data->bi.biFenceStatus) in pnv_eeh_get_and_dump_hub_diag()
1311 be64_to_cpu(data->bi.biLdcp0), in pnv_eeh_get_and_dump_hub_diag()
1312 be64_to_cpu(data->bi.biLdcp1), in pnv_eeh_get_and_dump_hub_diag()
1313 be64_to_cpu(data->bi.biLdcp2), in pnv_eeh_get_and_dump_hub_diag()
1314 be64_to_cpu(data->bi.biFenceStatus)); in pnv_eeh_get_and_dump_hub_diag()
1317 pr_info("P7IOC diag-data for CI Port %d\n\n", in pnv_eeh_get_and_dump_hub_diag()
1318 data->ci.ciPort); in pnv_eeh_get_and_dump_hub_diag()
1320 if (data->ci.ciPortStatus || data->ci.ciPortLdcp) in pnv_eeh_get_and_dump_hub_diag()
1322 be64_to_cpu(data->ci.ciPortStatus), in pnv_eeh_get_and_dump_hub_diag()
1323 be64_to_cpu(data->ci.ciPortLdcp)); in pnv_eeh_get_and_dump_hub_diag()
1326 pr_info("P7IOC diag-data for MISC\n\n"); in pnv_eeh_get_and_dump_hub_diag()
1330 pr_info("P7IOC diag-data for I2C\n\n"); in pnv_eeh_get_and_dump_hub_diag()
1334 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", in pnv_eeh_get_and_dump_hub_diag()
1335 __func__, phb->hub_id, data->type); in pnv_eeh_get_and_dump_hub_diag()
1342 struct pnv_phb *phb = hose->private_data; in pnv_eeh_get_pe()
1347 * If PHB supports compound PE, to fetch in pnv_eeh_get_pe()
1351 pnv_pe = &phb->ioda.pe_array[pe_no]; in pnv_eeh_get_pe()
1352 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { in pnv_eeh_get_pe()
1353 pnv_pe = pnv_pe->master; in pnv_eeh_get_pe()
1355 !(pnv_pe->flags & PNV_IODA_PE_MASTER)); in pnv_eeh_get_pe()
1356 pe_no = pnv_pe->pe_number; in pnv_eeh_get_pe()
1362 return -EEXIST; in pnv_eeh_get_pe()
1364 /* Freeze the (compound) PE */ in pnv_eeh_get_pe()
1366 if (!(dev_pe->state & EEH_PE_ISOLATED)) in pnv_eeh_get_pe()
1367 phb->freeze_pe(phb, pe_no); in pnv_eeh_get_pe()
1370 * At this point, we're sure the (compound) PE should in pnv_eeh_get_pe()
1374 dev_pe = dev_pe->parent; in pnv_eeh_get_pe()
1375 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { in pnv_eeh_get_pe()
1377 ret = eeh_ops->get_state(dev_pe, NULL); in pnv_eeh_get_pe()
1379 dev_pe = dev_pe->parent; in pnv_eeh_get_pe()
1385 if (!(dev_pe->state & EEH_PE_ISOLATED)) in pnv_eeh_get_pe()
1386 phb->freeze_pe(phb, dev_pe->addr); in pnv_eeh_get_pe()
1389 dev_pe = dev_pe->parent; in pnv_eeh_get_pe()
1396 * pnv_eeh_next_error - Retrieve next EEH error to handle
1427 phb = hose->private_data; in pnv_eeh_next_error()
1429 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) in pnv_eeh_next_error()
1432 rc = opal_pci_next_error(phb->opal_id, in pnv_eeh_next_error()
1437 __func__, hose->global_number, rc); in pnv_eeh_next_error()
1445 __func__, hose->global_number); in pnv_eeh_next_error()
1457 hose->global_number); in pnv_eeh_next_error()
1476 hose->global_number, in pnv_eeh_next_error()
1484 hose->global_number, in pnv_eeh_next_error()
1490 hose->global_number, in pnv_eeh_next_error()
1493 pnv_pci_dump_phb_diag_data(hose, phb_pe->data); in pnv_eeh_next_error()
1505 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", in pnv_eeh_next_error()
1506 hose->global_number, be64_to_cpu(frozen_pe_no)); in pnv_eeh_next_error()
1510 /* Dump PHB diag-data */ in pnv_eeh_next_error()
1511 rc = opal_pci_get_phb_diag_data2(phb->opal_id, in pnv_eeh_next_error()
1512 phb->diag_data, phb->diag_data_size); in pnv_eeh_next_error()
1515 phb->diag_data); in pnv_eeh_next_error()
1518 opal_pci_eeh_freeze_clear(phb->opal_id, in pnv_eeh_next_error()
1522 } else if ((*pe)->state & EEH_PE_ISOLATED || in pnv_eeh_next_error()
1528 (*pe)->addr, in pnv_eeh_next_error()
1529 (*pe)->phb->global_number); in pnv_eeh_next_error()
1552 !((*pe)->state & EEH_PE_ISOLATED)) { in pnv_eeh_next_error()
1557 pnv_pci_dump_phb_diag_data((*pe)->phb, in pnv_eeh_next_error()
1558 (*pe)->data); in pnv_eeh_next_error()
1566 parent_pe = (*pe)->parent; in pnv_eeh_next_error()
1569 if (parent_pe->type & EEH_PE_PHB) in pnv_eeh_next_error()
1573 state = eeh_ops->get_state(parent_pe, NULL); in pnv_eeh_next_error()
1578 parent_pe = parent_pe->parent; in pnv_eeh_next_error()
1608 return -EEXIST; in pnv_eeh_restore_config()
1610 if (edev->physfn) in pnv_eeh_restore_config()
1613 phb = edev->controller->private_data; in pnv_eeh_restore_config()
1614 ret = opal_pci_reinit(phb->opal_id, in pnv_eeh_restore_config()
1615 OPAL_REINIT_PCI_DEV, edev->bdfn); in pnv_eeh_restore_config()
1619 __func__, edev->bdfn, ret); in pnv_eeh_restore_config()
1620 return -EIO; in pnv_eeh_restore_config()
1643 * eeh_powernv_init - Register platform dependent EEH operations
1653 int ret = -EINVAL; in eeh_powernv_init()
1657 return -EINVAL; in eeh_powernv_init()
1669 phb = hose->private_data; in eeh_powernv_init()
1671 if (phb->model == PNV_PHB_MODEL_P7IOC) in eeh_powernv_init()
1674 if (phb->diag_data_size > max_diag_size) in eeh_powernv_init()
1675 max_diag_size = phb->diag_data_size; in eeh_powernv_init()