Lines Matching full:31
114 SAVE_GPR 31, 248, 1
128 SAVE_VRS 31, 176, 9
147 SAVE_VSX 31, 464, 9
163 RESTORE_VRS 31, 176, 9
182 RESTORE_VSX 31, 464, 9
201 RESTORE_GPR 31, 248, 1
354 xxlxor 31, 31, 31
443 vsrd 10, 14, 31
444 vsrd 11, 17, 31
448 vsrd 12, 18, 31
451 vsrd 11, 15, 31
458 vsrd 13, 6, 31
461 vsrd 10, 4, 31
464 vsrd 11, 7, 31
487 lvx 31, 14, 10 # v31 = 1a
571 vsrd 10, 14, 31 # >> 26
572 vsrd 11, 10, 31 # 12 bits left
581 vsrd 13, 12, 31 # >> 26, a4
598 vsrd 10, 14, 31 # >> 26
599 vsrd 11, 10, 31 # 12 bits left
608 vsrd 13, 12, 31 # >> 26, a4
623 divdu 31, 5, 9
625 cmpdi 31, 0
628 mtctr 31
645 vsrd 10, 14, 31
646 vsrd 11, 17, 31
650 vsrd 12, 18, 31
653 vsrd 11, 15, 31
660 vsrd 13, 6, 31
663 vsrd 10, 4, 31
666 vsrd 11, 7, 31
690 vsrd 21, 14, 31 # >> 26
691 vsrd 22, 21, 31 # 12 bits left
692 vsrd 10, 17, 31 # >> 26
693 vsrd 11, 10, 31 # 12 bits left
709 vsrd 24, 23, 31 # >> 26, a4
712 vsrd 13, 12, 31 # >> 26, a4
750 xxpermdi 41, 31, 46, 0
751 xxpermdi 42, 31, 47, 0
753 xxpermdi 36, 31, 36, 3
755 xxpermdi 37, 31, 37, 3
756 xxpermdi 43, 31, 48, 0
758 xxpermdi 38, 31, 38, 3
759 xxpermdi 44, 31, 49, 0
761 xxpermdi 39, 31, 39, 3
762 xxpermdi 45, 31, 50, 0
764 xxpermdi 40, 31, 40, 3
768 vsrd 10, 4, 31
769 vsrd 11, 7, 31
773 vsrd 12, 8, 31
776 vsrd 11, 5, 31
783 vsrd 13, 6, 31
786 vsrd 10, 4, 31
789 vsrd 11, 7, 31
793 vsrd 10, 5, 31
803 vsld 5, 5, 31
807 vsld 6, 6, 31
808 vsld 6, 6, 31
815 vsld 8, 8, 31
950 SAVE_GPR 31, 248, 1
966 divdu 31, 5, 30
968 mtctr 31
1016 RESTORE_GPR 31, 248, 1