Lines Matching full:have
88 bool "Have write through data caches"
105 bool "Have instruction l.ff1"
111 bool "Have instruction l.fl1"
117 bool "Have instruction l.mul for hardware multiply"
123 bool "Have instruction l.div for hardware divide"
129 bool "Have instruction l.cmov for conditional move"
142 bool "Have instruction l.ror for rotate right"
155 bool "Have instruction l.rori for rotate right with immediate"
168 bool "Have instructions l.ext* for sign extension"
191 This enables support for systems with more than one CPU. If you have
192 a system with only one CPU, say N. If you have a system with more
215 OpenRISC architecture makes it optional to have it implemented
216 in hardware and the OR1200 does not have it.
248 your kernel crashes this doesn't have any influence.