33 #include <linux/io.h>		/* need byte IO */
39 /* DMA Channel Register Offsets */
107 	int dev_id;		/* this channel is allocated if >= 0, */
109 	void __iomem *io;  member
159 	__raw_writel(DMA_BE0, chan->io + DMA_MODE_SET);  in enable_dma_buffer0()
168 	__raw_writel(DMA_BE1, chan->io + DMA_MODE_SET);  in enable_dma_buffer1()
176 	__raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);  in enable_dma_buffers()
185 	__raw_writel(DMA_GO, chan->io + DMA_MODE_SET);  in start_dma()
197 	__raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);  in halt_dma()
201 		if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT)  in halt_dma()
217 	__raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);  in disable_dma()
226 	return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;  in dma_halted()
229 /* Initialize a DMA channel. */
241 	__raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);  in init_dma()
243 	mode = chan->mode | (chan->dev_id << DMA_DID_BIT);  in init_dma()
244 	if (chan->irq)  in init_dma()
247 	__raw_writel(~mode, chan->io + DMA_MODE_CLEAR);  in init_dma()
248 	__raw_writel(mode,	 chan->io + DMA_MODE_SET);  in init_dma()
252  * Set mode for a specific DMA channel
266 	chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);  in set_dma_mode()
267 	chan->mode |= mode;  in set_dma_mode()
276 	return chan->mode;  in get_dma_mode()
284 		return -1;  in get_dma_active_buffer()
285 	return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;  in get_dma_active_buffer()
289  * Set the device FIFO address for a specific DMA channel - only
300 	if (chan->mode & DMA_DS)	/* second bank of device IDs */  in set_dma_fifo_addr()
303 	if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)  in set_dma_fifo_addr()
306 	__raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);  in set_dma_fifo_addr()
318 	__raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);  in clear_dma_done0()
327 	__raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);  in clear_dma_done1()
331  * This does nothing - not applicable to Au1000 DMA.
338  * Set Buffer 0 transfer address for specific DMA channel.
346 	__raw_writel(a, chan->io + DMA_BUFFER0_START);  in set_dma_addr0()
350  * Set Buffer 1 transfer address for specific DMA channel.
358 	__raw_writel(a, chan->io + DMA_BUFFER1_START);  in set_dma_addr1()
363  * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
372 	__raw_writel(count, chan->io + DMA_BUFFER0_COUNT);  in set_dma_count0()
376  * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
385 	__raw_writel(count, chan->io + DMA_BUFFER1_COUNT);  in set_dma_count1()
389  * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
398 	__raw_writel(count, chan->io + DMA_BUFFER0_COUNT);  in set_dma_count()
399 	__raw_writel(count, chan->io + DMA_BUFFER1_COUNT);  in set_dma_count()
404  * Returns -1 if neither or both done bits set.
412 	return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);  in get_dma_buffer_done()
417  * Returns the DMA channel's Buffer Done IRQ number.
424 		return -1;  in get_dma_done_irq()
425 	return chan->irq;  in get_dma_done_irq()
439 	curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?  in get_dma_residue()
442 	count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;  in get_dma_residue()
444 	if ((chan->mode & DMA_DW_MASK) == DMA_DW16)  in get_dma_residue()
446 	else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)  in get_dma_residue()