Lines Matching +full:auxclk +full:- +full:fs +full:- +full:ratio
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 stdout-path = "serial2:115200n8";
25 reserved_memory: reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
32 no-map;
35 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
36 compatible = "shared-dma-pool";
38 no-map;
41 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
42 compatible = "shared-dma-pool";
44 no-map;
47 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
48 compatible = "shared-dma-pool";
50 no-map;
53 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
54 compatible = "shared-dma-pool";
56 no-map;
59 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
60 compatible = "shared-dma-pool";
62 no-map;
65 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
66 compatible = "shared-dma-pool";
68 no-map;
71 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
72 compatible = "shared-dma-pool";
74 no-map;
77 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
78 compatible = "shared-dma-pool";
80 no-map;
83 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
84 compatible = "shared-dma-pool";
86 no-map;
89 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
90 compatible = "shared-dma-pool";
92 no-map;
95 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
96 compatible = "shared-dma-pool";
98 no-map;
101 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
102 compatible = "shared-dma-pool";
104 no-map;
107 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
108 compatible = "shared-dma-pool";
110 no-map;
113 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
114 compatible = "shared-dma-pool";
116 no-map;
119 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
120 compatible = "shared-dma-pool";
122 no-map;
125 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
126 compatible = "shared-dma-pool";
128 no-map;
131 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
132 compatible = "shared-dma-pool";
134 no-map;
137 c71_0_memory_region: c71-memory@a8100000 {
138 compatible = "shared-dma-pool";
140 no-map;
143 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
144 compatible = "shared-dma-pool";
146 no-map;
149 c71_1_memory_region: c71-memory@a9100000 {
150 compatible = "shared-dma-pool";
152 no-map;
155 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
156 compatible = "shared-dma-pool";
158 no-map;
161 c71_2_memory_region: c71-memory@aa100000 {
162 compatible = "shared-dma-pool";
164 no-map;
168 evm_12v0: regulator-evm12v0 {
170 compatible = "regulator-fixed";
171 regulator-name = "evm_12v0";
172 regulator-min-microvolt = <12000000>;
173 regulator-max-microvolt = <12000000>;
174 regulator-always-on;
175 regulator-boot-on;
178 vsys_3v3: regulator-vsys3v3 {
180 compatible = "regulator-fixed";
181 regulator-name = "vsys_3v3";
182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <3300000>;
184 vin-supply = <&evm_12v0>;
185 regulator-always-on;
186 regulator-boot-on;
189 vsys_5v0: regulator-vsys5v0 {
191 compatible = "regulator-fixed";
192 regulator-name = "vsys_5v0";
193 regulator-min-microvolt = <5000000>;
194 regulator-max-microvolt = <5000000>;
195 vin-supply = <&evm_12v0>;
196 regulator-always-on;
197 regulator-boot-on;
200 vdd_mmc1: regulator-sd {
202 compatible = "regulator-fixed";
203 regulator-name = "vdd_mmc1";
204 regulator-min-microvolt = <3300000>;
205 regulator-max-microvolt = <3300000>;
206 regulator-boot-on;
207 enable-active-high;
208 vin-supply = <&vsys_3v3>;
212 vdd_sd_dv: regulator-TLV71033 {
214 compatible = "regulator-gpio";
215 regulator-name = "tlv71033";
216 pinctrl-names = "default";
217 pinctrl-0 = <&vdd_sd_dv_pins_default>;
218 regulator-min-microvolt = <1800000>;
219 regulator-max-microvolt = <3300000>;
220 regulator-boot-on;
221 vin-supply = <&vsys_5v0>;
227 dp0_pwr_3v3: regulator-dp0-prw {
228 compatible = "regulator-fixed";
229 regulator-name = "dp0-pwr";
230 regulator-min-microvolt = <3300000>;
231 regulator-max-microvolt = <3300000>;
233 enable-active-high;
236 dp0: connector-dp0 {
237 compatible = "dp-connector";
239 type = "full-size";
240 dp-pwr-supply = <&dp0_pwr_3v3>;
244 remote-endpoint = <&dp0_out>;
249 transceiver0: can-phy0 {
251 #phy-cells = <0>;
252 max-bitrate = <5000000>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
255 standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>;
258 transceiver1: can-phy1 {
260 #phy-cells = <0>;
261 max-bitrate = <5000000>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
264 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
267 transceiver2: can-phy2 {
270 #phy-cells = <0>;
271 max-bitrate = <5000000>;
274 transceiver3: can-phy3 {
276 #phy-cells = <0>;
277 max-bitrate = <5000000>;
278 standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
279 mux-states = <&mux1 1>;
282 mux1: mux-controller {
283 compatible = "gpio-mux";
284 #mux-state-cells = <1>;
285 mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>;
286 idle-state = <1>;
290 compatible = "ti,j7200-cpb-audio";
291 model = "j784s4-cpb";
293 ti,cpb-mcasp = <&mcasp0>;
294 ti,cpb-codec = <&pcm3168a_1>;
298 clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000",
299 "cpb-codec-scki", "cpb-codec-scki-48000";
308 main_cpsw2g_default_pins: main-cpsw2g-default-pins {
309 pinctrl-single,pins = <
325 main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins {
326 pinctrl-single,pins = <
332 main_uart8_pins_default: main-uart8-default-pins {
333 bootph-all;
334 pinctrl-single,pins = <
342 main_i2c0_pins_default: main-i2c0-default-pins {
343 pinctrl-single,pins = <
349 main_i2c5_pins_default: main-i2c5-default-pins {
350 pinctrl-single,pins = <
356 main_mmc1_pins_default: main-mmc1-default-pins {
357 bootph-all;
358 pinctrl-single,pins = <
370 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
371 pinctrl-single,pins = <
376 dp0_pins_default: dp0-default-pins {
377 pinctrl-single,pins = <
382 main_i2c4_pins_default: main-i2c4-default-pins {
383 pinctrl-single,pins = <
389 main_mcan4_pins_default: main-mcan4-default-pins {
390 pinctrl-single,pins = <
396 main_mcan16_pins_default: main-mcan16-default-pins {
397 pinctrl-single,pins = <
403 main_usbss0_pins_default: main-usbss0-default-pins {
404 bootph-all;
405 pinctrl-single,pins = <
410 main_i2c3_pins_default: main-i2c3-default-pins {
411 pinctrl-single,pins = <
417 main_mcasp0_pins_default: main-mcasp0-default-pins {
418 pinctrl-single,pins = <
426 audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
427 pinctrl-single,pins = <
434 wkup_uart0_pins_default: wkup-uart0-default-pins {
435 bootph-all;
436 pinctrl-single,pins = <
442 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
443 bootph-all;
444 pinctrl-single,pins = <
450 mcu_uart0_pins_default: mcu-uart0-default-pins {
451 bootph-all;
452 pinctrl-single,pins = <
460 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
461 pinctrl-single,pins = <
477 mcu_mdio_pins_default: mcu-mdio-default-pins {
478 pinctrl-single,pins = <
484 mcu_adc0_pins_default: mcu-adc0-default-pins {
485 pinctrl-single,pins = <
497 mcu_adc1_pins_default: mcu-adc1-default-pins {
498 pinctrl-single,pins = <
510 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
511 pinctrl-single,pins = <
517 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
518 pinctrl-single,pins = <
524 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
525 pinctrl-single,pins = <
530 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
531 pinctrl-single,pins = <
540 pmic_irq_pins_default: pmic-irq-default-pins {
541 pinctrl-single,pins = <
549 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
550 bootph-all;
551 pinctrl-single,pins = <
568 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins {
569 bootph-all;
570 pinctrl-single,pins = <
576 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
577 bootph-all;
578 pinctrl-single,pins = <
594 pinctrl-names = "default";
595 pinctrl-0 = <&wkup_uart0_pins_default>;
599 bootph-all;
601 pinctrl-names = "default";
602 pinctrl-0 = <&wkup_i2c0_pins_default>;
603 clock-frequency = <400000>;
606 /* CAV24C256WE-GT3 */
612 compatible = "ti,tps6594-q1";
614 system-power-controller;
615 pinctrl-names = "default";
616 pinctrl-0 = <&pmic_irq_pins_default>;
617 interrupt-parent = <&wkup_gpio0>;
619 gpio-controller;
620 #gpio-cells = <2>;
621 ti,primary-pmic;
622 buck12-supply = <&vsys_3v3>;
623 buck3-supply = <&vsys_3v3>;
624 buck4-supply = <&vsys_3v3>;
625 buck5-supply = <&vsys_3v3>;
626 ldo1-supply = <&vsys_3v3>;
627 ldo2-supply = <&vsys_3v3>;
628 ldo3-supply = <&vsys_3v3>;
629 ldo4-supply = <&vsys_3v3>;
633 regulator-name = "vdd_ddr_1v1";
634 regulator-min-microvolt = <1100000>;
635 regulator-max-microvolt = <1100000>;
636 regulator-boot-on;
637 regulator-always-on;
638 bootph-all;
642 regulator-name = "vdd_ram_0v85";
643 regulator-min-microvolt = <850000>;
644 regulator-max-microvolt = <850000>;
645 regulator-boot-on;
646 regulator-always-on;
647 bootph-all;
651 regulator-name = "vdd_io_1v8";
652 regulator-min-microvolt = <1800000>;
653 regulator-max-microvolt = <1800000>;
654 regulator-boot-on;
655 regulator-always-on;
656 bootph-all;
660 regulator-name = "vdd_mcu_0v85";
661 regulator-min-microvolt = <850000>;
662 regulator-max-microvolt = <850000>;
663 regulator-boot-on;
664 regulator-always-on;
665 bootph-all;
669 regulator-name = "vdd_mcuio_1v8";
670 regulator-min-microvolt = <1800000>;
671 regulator-max-microvolt = <1800000>;
672 regulator-boot-on;
673 regulator-always-on;
674 bootph-all;
678 regulator-name = "vdd_mcuio_3v3";
679 regulator-min-microvolt = <3300000>;
680 regulator-max-microvolt = <3300000>;
681 regulator-boot-on;
682 regulator-always-on;
683 bootph-all;
687 regulator-name = "vds_dll_0v8";
688 regulator-min-microvolt = <800000>;
689 regulator-max-microvolt = <800000>;
690 regulator-boot-on;
691 regulator-always-on;
692 bootph-all;
696 regulator-name = "vda_mcu_1v8";
697 regulator-min-microvolt = <1800000>;
698 regulator-max-microvolt = <1800000>;
699 regulator-boot-on;
700 regulator-always-on;
701 bootph-all;
709 bootph-pre-ram;
710 regulator-name = "VDD_CPU_AVS";
711 regulator-min-microvolt = <750000>;
712 regulator-max-microvolt = <1330000>;
713 regulator-boot-on;
714 regulator-always-on;
720 regulator-name = "VDD_CORE_0V8";
721 regulator-min-microvolt = <760000>;
722 regulator-max-microvolt = <840000>;
723 regulator-boot-on;
724 regulator-always-on;
729 bootph-all;
731 pinctrl-names = "default";
732 pinctrl-0 = <&mcu_uart0_pins_default>;
736 bootph-all;
738 pinctrl-names = "default";
739 pinctrl-0 = <&main_uart8_pins_default>;
752 pinctrl-names = "default";
753 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>;
756 compatible = "jedec,spi-nor";
758 spi-tx-bus-width = <8>;
759 spi-rx-bus-width = <8>;
760 spi-max-frequency = <25000000>;
761 cdns,tshsl-ns = <60>;
762 cdns,tsd2d-ns = <60>;
763 cdns,tchsh-ns = <60>;
764 cdns,tslch-ns = <60>;
765 cdns,read-delay = <4>;
768 compatible = "fixed-partitions";
769 #address-cells = <1>;
770 #size-cells = <1>;
783 label = "ospi.u-boot";
803 bootph-all;
813 pinctrl-names = "default";
814 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
817 compatible = "jedec,spi-nor";
819 spi-tx-bus-width = <1>;
820 spi-rx-bus-width = <4>;
821 spi-max-frequency = <40000000>;
822 cdns,tshsl-ns = <60>;
823 cdns,tsd2d-ns = <60>;
824 cdns,tchsh-ns = <60>;
825 cdns,tslch-ns = <60>;
826 cdns,read-delay = <2>;
829 compatible = "fixed-partitions";
830 #address-cells = <1>;
831 #size-cells = <1>;
844 label = "qspi.u-boot";
864 bootph-all;
875 pinctrl-names = "default";
876 pinctrl-0 = <&main_i2c0_pins_default>;
878 clock-frequency = <400000>;
883 gpio-controller;
884 #gpio-cells = <2>;
885 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ",
891 p12-hog {
892 /* P12 - AUDIO_MUX_SEL */
893 gpio-hog;
895 output-low;
896 line-name = "AUDIO_MUX_SEL";
903 gpio-controller;
904 #gpio-cells = <2>;
905 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN",
914 p13-hog {
915 /* P13 - CANUART_MUX_SEL0 */
916 gpio-hog;
918 output-high;
919 line-name = "CANUART_MUX_SEL0";
922 p15-hog {
923 /* P15 - CANUART_MUX1_SEL1 */
924 gpio-hog;
926 output-high;
927 line-name = "CANUART_MUX1_SEL1";
933 pinctrl-names = "default";
934 pinctrl-0 = <&main_i2c5_pins_default>;
935 clock-frequency = <400000>;
941 gpio-controller;
942 #gpio-cells = <2>;
943 gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0",
951 bootph-all;
954 non-removable;
955 ti,driver-strength-ohm = <50>;
956 disable-wp;
960 bootph-all;
963 pinctrl-0 = <&main_mmc1_pins_default>;
964 pinctrl-names = "default";
965 disable-wp;
966 vmmc-supply = <&vdd_mmc1>;
967 vqmmc-supply = <&vdd_sd_dv>;
976 pinctrl-names = "default";
977 pinctrl-0 = <&mcu_cpsw_pins_default>;
981 pinctrl-names = "default";
982 pinctrl-0 = <&mcu_mdio_pins_default>;
984 mcu_phy0: ethernet-phy@0 {
986 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
987 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
988 ti,min-output-impedance;
994 phy-mode = "rgmii-rxid";
995 phy-handle = <&mcu_phy0>;
999 pinctrl-names = "default";
1000 pinctrl-0 = <&main_cpsw2g_default_pins>;
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&main_cpsw2g_mdio_default_pins>;
1009 main_cpsw1_phy0: ethernet-phy@0 {
1011 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
1012 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
1013 ti,min-output-impedance;
1018 phy-mode = "rgmii-rxid";
1019 phy-handle = <&main_cpsw1_phy0>;
1027 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
1028 ti,mbox-rx = <0 0 0>;
1029 ti,mbox-tx = <1 0 0>;
1032 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
1033 ti,mbox-rx = <2 0 0>;
1034 ti,mbox-tx = <3 0 0>;
1042 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
1043 ti,mbox-rx = <0 0 0>;
1044 ti,mbox-tx = <1 0 0>;
1047 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
1048 ti,mbox-rx = <2 0 0>;
1049 ti,mbox-tx = <3 0 0>;
1057 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
1058 ti,mbox-rx = <0 0 0>;
1059 ti,mbox-tx = <1 0 0>;
1062 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
1063 ti,mbox-rx = <2 0 0>;
1064 ti,mbox-tx = <3 0 0>;
1072 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
1073 ti,mbox-rx = <0 0 0>;
1074 ti,mbox-tx = <1 0 0>;
1077 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
1078 ti,mbox-rx = <2 0 0>;
1079 ti,mbox-tx = <3 0 0>;
1087 mbox_c71_0: mbox-c71-0 {
1088 ti,mbox-rx = <0 0 0>;
1089 ti,mbox-tx = <1 0 0>;
1092 mbox_c71_1: mbox-c71-1 {
1093 ti,mbox-rx = <2 0 0>;
1094 ti,mbox-tx = <3 0 0>;
1102 mbox_c71_2: mbox-c71-2 {
1103 ti,mbox-rx = <0 0 0>;
1104 ti,mbox-tx = <1 0 0>;
1111 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
1118 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
1123 ti,cluster-mode = <0>;
1127 ti,cluster-mode = <0>;
1131 ti,cluster-mode = <0>;
1178 memory-region = <&main_r5fss0_core0_dma_memory_region>,
1185 memory-region = <&main_r5fss0_core1_dma_memory_region>,
1192 memory-region = <&main_r5fss1_core0_dma_memory_region>,
1199 memory-region = <&main_r5fss1_core1_dma_memory_region>,
1206 memory-region = <&main_r5fss2_core0_dma_memory_region>,
1213 memory-region = <&main_r5fss2_core1_dma_memory_region>,
1220 memory-region = <&c71_0_dma_memory_region>,
1227 memory-region = <&c71_1_dma_memory_region>,
1234 memory-region = <&c71_2_dma_memory_region>,
1239 pinctrl-0 = <&mcu_adc0_pins_default>;
1240 pinctrl-names = "default";
1243 ti,adc-channels = <0 1 2 3 4 5 6 7>;
1248 pinctrl-0 = <&mcu_adc1_pins_default>;
1249 pinctrl-names = "default";
1252 ti,adc-channels = <0 1 2 3 4 5 6 7>;
1258 clock-frequency = <100000000>;
1263 assigned-clocks = <&k3_clks 218 2>,
1267 assigned-clock-parents = <&k3_clks 218 3>,
1278 cdns,num-lanes = <2>;
1279 #phy-cells = <0>;
1280 cdns,phy-type = <PHY_TYPE_PCIE>;
1286 cdns,num-lanes = <1>;
1287 #phy-cells = <0>;
1288 cdns,phy-type = <PHY_TYPE_USB3>;
1298 idle-states = <0>; /* USB0 to SERDES lane 3 */
1303 pinctrl-0 = <&main_usbss0_pins_default>;
1304 pinctrl-names = "default";
1305 ti,vbus-divider;
1310 maximum-speed = "super-speed";
1312 phy-names = "cdns3,usb3-phy";
1323 cdns,num-lanes = <4>;
1324 #phy-cells = <0>;
1325 cdns,phy-type = <PHY_TYPE_DP>;
1333 pinctrl-names = "default";
1334 pinctrl-0 = <&dp0_pins_default>;
1336 phy-names = "dpphy";
1343 remote-endpoint = <&dp0_in>;
1350 pinctrl-names = "default";
1351 pinctrl-0 = <&main_i2c4_pins_default>;
1352 clock-frequency = <400000>;
1357 gpio-controller;
1358 #gpio-cells = <2>;
1367 remote-endpoint = <&dpi0_out>;
1375 remote-endpoint = <&dp0_connector_in>;
1382 pinctrl-names = "default";
1383 pinctrl-0 = <&mcu_mcan0_pins_default>;
1389 pinctrl-names = "default";
1390 pinctrl-0 = <&mcu_mcan1_pins_default>;
1396 pinctrl-names = "default";
1397 pinctrl-0 = <&main_mcan16_pins_default>;
1403 pinctrl-names = "default";
1404 pinctrl-0 = <&main_mcan4_pins_default>;
1410 num-lanes = <2>;
1411 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
1413 phy-names = "pcie-phy";
1421 cdns,num-lanes = <4>;
1422 #phy-cells = <0>;
1423 cdns,phy-type = <PHY_TYPE_PCIE>;
1435 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
1437 phy-names = "pcie-phy";
1442 pinctrl-names = "default";
1443 pinctrl-0 = <&audio_ext_refclk1_pins_default>;
1448 pinctrl-names = "default";
1449 pinctrl-0 = <&main_i2c3_pins_default>;
1450 clock-frequency = <400000>;
1455 gpio-controller;
1456 #gpio-cells = <2>;
1459 pcm3168a_1: audio-codec@44 {
1462 #sound-dai-cells = <1>;
1463 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
1465 clock-names = "scki";
1466 VDD1-supply = <&vsys_3v3>;
1467 VDD2-supply = <&vsys_3v3>;
1468 VCCAD1-supply = <&vsys_5v0>;
1469 VCCAD2-supply = <&vsys_5v0>;
1470 VCCDA1-supply = <&vsys_5v0>;
1471 VCCDA2-supply = <&vsys_5v0>;
1477 #sound-dai-cells = <0>;
1478 pinctrl-names = "default";
1479 pinctrl-0 = <&main_mcasp0_pins_default>;
1480 op-mode = <0>; /* MCASP_IIS_MODE */
1481 tdm-slots = <2>;
1482 auxclk-fs-ratio = <256>;
1483 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */