Lines Matching +full:assigned +full:- +full:clock +full:- +full:parents
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
24 #size-cells = <1>;
27 atf-sram@0 {
31 tifs-sram@1f0000 {
35 l3cache-sram@200000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
43 #address-cells = <1>;
44 #size-cells = <1>;
47 usb_serdes_mux: mux-controller@0 {
48 compatible = "reg-mux";
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
55 compatible = "ti,am654-phy-gmii-sel";
57 #phy-cells = <1>;
60 serdes_ln_ctrl: mux-controller@80 {
61 compatible = "reg-mux";
63 #mux-control-cells = <1>;
64 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
68 ehrpwm_tbclk: clock-controller@140 {
69 compatible = "ti,am654-ehrpwm-tbclk";
71 #clock-cells = <1>;
76 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
77 #pwm-cells = <3>;
79 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
81 clock-names = "tbclk", "fck";
86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
87 #pwm-cells = <3>;
89 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
91 clock-names = "tbclk", "fck";
96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
97 #pwm-cells = <3>;
99 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
101 clock-names = "tbclk", "fck";
106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
107 #pwm-cells = <3>;
109 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
111 clock-names = "tbclk", "fck";
116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
117 #pwm-cells = <3>;
119 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
121 clock-names = "tbclk", "fck";
126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
127 #pwm-cells = <3>;
129 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
131 clock-names = "tbclk", "fck";
135 gic500: interrupt-controller@1800000 {
136 compatible = "arm,gic-v3";
137 #address-cells = <2>;
138 #size-cells = <2>;
140 #interrupt-cells = <3>;
141 interrupt-controller;
151 gic_its: msi-controller@1820000 {
152 compatible = "arm,gic-v3-its";
154 socionext,synquacer-pre-its = <0x1000000 0x400000>;
155 msi-controller;
156 #msi-cells = <1>;
160 main_gpio_intr: interrupt-controller@a00000 {
161 compatible = "ti,sci-intr";
163 ti,intr-trigger-type = <1>;
164 interrupt-controller;
165 interrupt-parent = <&gic500>;
166 #interrupt-cells = <1>;
168 ti,sci-dev-id = <148>;
169 ti,interrupt-ranges = <8 392 56>;
173 compatible = "pinctrl-single";
176 #pinctrl-cells = <1>;
177 pinctrl-single,register-width = <32>;
178 pinctrl-single,function-mask = <0xffffffff>;
183 compatible = "pinctrl-single";
185 #pinctrl-cells = <1>;
186 pinctrl-single,register-width = <32>;
187 pinctrl-single,function-mask = <0x00000007>;
192 compatible = "pinctrl-single";
194 #pinctrl-cells = <1>;
195 pinctrl-single,register-width = <32>;
196 pinctrl-single,function-mask = <0x0000001f>;
200 compatible = "ti,j721e-sa2ul";
202 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
203 #address-cells = <2>;
204 #size-cells = <2>;
209 dma-names = "tx", "rx1", "rx2";
212 compatible = "inside-secure,safexcel-eip76";
219 compatible = "ti,am654-timer";
223 clock-names = "fck";
224 assigned-clocks = <&k3_clks 63 1>;
225 assigned-clock-parents = <&k3_clks 63 2>;
226 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
227 ti,timer-pwm;
231 compatible = "ti,am654-timer";
235 clock-names = "fck";
236 assigned-clocks = <&k3_clks 64 1>;
237 assigned-clock-parents = <&k3_clks 64 2>;
238 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
239 ti,timer-pwm;
243 compatible = "ti,am654-timer";
247 clock-names = "fck";
248 assigned-clocks = <&k3_clks 65 1>;
249 assigned-clock-parents = <&k3_clks 65 2>;
250 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
251 ti,timer-pwm;
255 compatible = "ti,am654-timer";
259 clock-names = "fck";
260 assigned-clocks = <&k3_clks 66 1>;
261 assigned-clock-parents = <&k3_clks 66 2>;
262 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
263 ti,timer-pwm;
267 compatible = "ti,am654-timer";
271 clock-names = "fck";
272 assigned-clocks = <&k3_clks 67 1>;
273 assigned-clock-parents = <&k3_clks 67 2>;
274 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
275 ti,timer-pwm;
279 compatible = "ti,am654-timer";
283 clock-names = "fck";
284 assigned-clocks = <&k3_clks 68 1>;
285 assigned-clock-parents = <&k3_clks 68 2>;
286 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
287 ti,timer-pwm;
291 compatible = "ti,am654-timer";
295 clock-names = "fck";
296 assigned-clocks = <&k3_clks 69 1>;
297 assigned-clock-parents = <&k3_clks 69 2>;
298 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
299 ti,timer-pwm;
303 compatible = "ti,am654-timer";
307 clock-names = "fck";
308 assigned-clocks = <&k3_clks 70 1>;
309 assigned-clock-parents = <&k3_clks 70 2>;
310 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
311 ti,timer-pwm;
315 compatible = "ti,am654-timer";
319 clock-names = "fck";
320 assigned-clocks = <&k3_clks 71 1>;
321 assigned-clock-parents = <&k3_clks 71 2>;
322 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
323 ti,timer-pwm;
327 compatible = "ti,am654-timer";
331 clock-names = "fck";
332 assigned-clocks = <&k3_clks 72 1>;
333 assigned-clock-parents = <&k3_clks 72 2>;
334 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
335 ti,timer-pwm;
339 compatible = "ti,am654-timer";
343 clock-names = "fck";
344 assigned-clocks = <&k3_clks 73 1>;
345 assigned-clock-parents = <&k3_clks 73 2>;
346 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
347 ti,timer-pwm;
351 compatible = "ti,am654-timer";
355 clock-names = "fck";
356 assigned-clocks = <&k3_clks 74 1>;
357 assigned-clock-parents = <&k3_clks 74 2>;
358 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
359 ti,timer-pwm;
363 compatible = "ti,am654-timer";
367 clock-names = "fck";
368 assigned-clocks = <&k3_clks 75 1>;
369 assigned-clock-parents = <&k3_clks 75 2>;
370 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
371 ti,timer-pwm;
375 compatible = "ti,am654-timer";
379 clock-names = "fck";
380 assigned-clocks = <&k3_clks 76 1>;
381 assigned-clock-parents = <&k3_clks 76 2>;
382 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
383 ti,timer-pwm;
387 compatible = "ti,am654-timer";
391 clock-names = "fck";
392 assigned-clocks = <&k3_clks 77 1>;
393 assigned-clock-parents = <&k3_clks 77 2>;
394 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
395 ti,timer-pwm;
399 compatible = "ti,am654-timer";
403 clock-names = "fck";
404 assigned-clocks = <&k3_clks 78 1>;
405 assigned-clock-parents = <&k3_clks 78 2>;
406 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
407 ti,timer-pwm;
411 compatible = "ti,am654-timer";
415 clock-names = "fck";
416 assigned-clocks = <&k3_clks 79 1>;
417 assigned-clock-parents = <&k3_clks 79 2>;
418 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
419 ti,timer-pwm;
423 compatible = "ti,am654-timer";
427 clock-names = "fck";
428 assigned-clocks = <&k3_clks 80 1>;
429 assigned-clock-parents = <&k3_clks 80 2>;
430 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
431 ti,timer-pwm;
435 compatible = "ti,am654-timer";
439 clock-names = "fck";
440 assigned-clocks = <&k3_clks 81 1>;
441 assigned-clock-parents = <&k3_clks 81 2>;
442 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
443 ti,timer-pwm;
447 compatible = "ti,am654-timer";
451 clock-names = "fck";
452 assigned-clocks = <&k3_clks 82 1>;
453 assigned-clock-parents = <&k3_clks 82 2>;
454 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
455 ti,timer-pwm;
459 compatible = "ti,j721e-uart", "ti,am654-uart";
463 clock-names = "fclk";
464 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
469 compatible = "ti,j721e-uart", "ti,am654-uart";
473 clock-names = "fclk";
474 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
479 compatible = "ti,j721e-uart", "ti,am654-uart";
483 clock-names = "fclk";
484 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
489 compatible = "ti,j721e-uart", "ti,am654-uart";
493 clock-names = "fclk";
494 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
499 compatible = "ti,j721e-uart", "ti,am654-uart";
503 clock-names = "fclk";
504 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
509 compatible = "ti,j721e-uart", "ti,am654-uart";
513 clock-names = "fclk";
514 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
519 compatible = "ti,j721e-uart", "ti,am654-uart";
523 clock-names = "fclk";
524 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
529 compatible = "ti,j721e-uart", "ti,am654-uart";
533 clock-names = "fclk";
534 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
539 compatible = "ti,j721e-uart", "ti,am654-uart";
543 clock-names = "fclk";
544 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
549 compatible = "ti,j721e-uart", "ti,am654-uart";
553 clock-names = "fclk";
554 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
559 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-parent = <&main_gpio_intr>;
565 interrupt-controller;
566 #interrupt-cells = <2>;
568 ti,davinci-gpio-unbanked = <0>;
569 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
571 clock-names = "gpio";
576 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
578 gpio-controller;
579 #gpio-cells = <2>;
580 interrupt-parent = <&main_gpio_intr>;
582 interrupt-controller;
583 #interrupt-cells = <2>;
585 ti,davinci-gpio-unbanked = <0>;
586 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
588 clock-names = "gpio";
593 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
595 gpio-controller;
596 #gpio-cells = <2>;
597 interrupt-parent = <&main_gpio_intr>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
602 ti,davinci-gpio-unbanked = <0>;
603 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
605 clock-names = "gpio";
610 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
612 gpio-controller;
613 #gpio-cells = <2>;
614 interrupt-parent = <&main_gpio_intr>;
616 interrupt-controller;
617 #interrupt-cells = <2>;
619 ti,davinci-gpio-unbanked = <0>;
620 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
622 clock-names = "gpio";
627 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
630 #address-cells = <1>;
631 #size-cells = <0>;
633 clock-names = "fck";
634 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
638 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
641 #address-cells = <1>;
642 #size-cells = <0>;
644 clock-names = "fck";
645 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
650 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
653 #address-cells = <1>;
654 #size-cells = <0>;
656 clock-names = "fck";
657 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
662 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
665 #address-cells = <1>;
666 #size-cells = <0>;
668 clock-names = "fck";
669 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
674 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
677 #address-cells = <1>;
678 #size-cells = <0>;
680 clock-names = "fck";
681 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
686 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
689 #address-cells = <1>;
690 #size-cells = <0>;
692 clock-names = "fck";
693 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
698 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
701 #address-cells = <1>;
702 #size-cells = <0>;
704 clock-names = "fck";
705 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
709 vpu: video-codec@4210000 {
710 compatible = "ti,j721s2-wave521c", "cnm,wave521c";
714 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
718 compatible = "ti,j721e-sdhci-8bit";
722 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
724 clock-names = "clk_ahb", "clk_xin";
725 assigned-clocks = <&k3_clks 98 1>;
726 assigned-clock-parents = <&k3_clks 98 2>;
727 bus-width = <8>;
728 ti,otap-del-sel-legacy = <0x0>;
729 ti,otap-del-sel-mmc-hs = <0x0>;
730 ti,otap-del-sel-ddr52 = <0x6>;
731 ti,otap-del-sel-hs200 = <0x8>;
732 ti,otap-del-sel-hs400 = <0x5>;
733 ti,itap-del-sel-legacy = <0x10>;
734 ti,itap-del-sel-mmc-hs = <0xa>;
735 ti,strobe-sel = <0x77>;
736 ti,clkbuf-sel = <0x7>;
737 ti,trm-icp = <0x8>;
738 mmc-ddr-1_8v;
739 mmc-hs200-1_8v;
740 mmc-hs400-1_8v;
741 dma-coherent;
746 compatible = "ti,j721e-sdhci-4bit";
750 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
752 clock-names = "clk_ahb", "clk_xin";
753 assigned-clocks = <&k3_clks 99 1>;
754 assigned-clock-parents = <&k3_clks 99 2>;
755 bus-width = <4>;
756 ti,otap-del-sel-legacy = <0x0>;
757 ti,otap-del-sel-sd-hs = <0x0>;
758 ti,otap-del-sel-sdr12 = <0xf>;
759 ti,otap-del-sel-sdr25 = <0xf>;
760 ti,otap-del-sel-sdr50 = <0xc>;
761 ti,otap-del-sel-sdr104 = <0x5>;
762 ti,otap-del-sel-ddr50 = <0xc>;
763 ti,itap-del-sel-legacy = <0x0>;
764 ti,itap-del-sel-sd-hs = <0x0>;
765 ti,itap-del-sel-sdr12 = <0x0>;
766 ti,itap-del-sel-sdr25 = <0x0>;
767 ti,itap-del-sel-ddr50 = <0x2>;
768 ti,clkbuf-sel = <0x7>;
769 ti,trm-icp = <0x8>;
770 dma-coherent;
775 compatible = "simple-bus";
776 #address-cells = <2>;
777 #size-cells = <2>;
779 ti,sci-dev-id = <224>;
780 dma-coherent;
781 dma-ranges;
783 main_navss_intr: interrupt-controller@310e0000 {
784 compatible = "ti,sci-intr";
786 ti,intr-trigger-type = <4>;
787 interrupt-controller;
788 interrupt-parent = <&gic500>;
789 #interrupt-cells = <1>;
791 ti,sci-dev-id = <227>;
792 ti,interrupt-ranges = <0 64 64>,
797 main_udmass_inta: msi-controller@33d00000 {
798 compatible = "ti,sci-inta";
800 interrupt-controller;
801 #interrupt-cells = <0>;
802 interrupt-parent = <&main_navss_intr>;
803 msi-controller;
805 ti,sci-dev-id = <265>;
806 ti,interrupt-ranges = <0 0 256>;
807 ti,unmapped-event-sources = <&main_bcdma_csi>;
811 compatible = "ti,am654-secure-proxy";
812 #mbox-cells = <1>;
813 reg-names = "target_data", "rt", "scfg";
817 interrupt-names = "rx_011";
819 bootph-all;
823 compatible = "ti,am654-hwspinlock";
825 #hwlock-cells = <1>;
829 compatible = "ti,am654-mailbox";
831 #mbox-cells = <1>;
832 ti,mbox-num-users = <4>;
833 ti,mbox-num-fifos = <16>;
834 interrupt-parent = <&main_navss_intr>;
839 compatible = "ti,am654-mailbox";
841 #mbox-cells = <1>;
842 ti,mbox-num-users = <4>;
843 ti,mbox-num-fifos = <16>;
844 interrupt-parent = <&main_navss_intr>;
849 compatible = "ti,am654-mailbox";
851 #mbox-cells = <1>;
852 ti,mbox-num-users = <4>;
853 ti,mbox-num-fifos = <16>;
854 interrupt-parent = <&main_navss_intr>;
859 compatible = "ti,am654-mailbox";
861 #mbox-cells = <1>;
862 ti,mbox-num-users = <4>;
863 ti,mbox-num-fifos = <16>;
864 interrupt-parent = <&main_navss_intr>;
869 compatible = "ti,am654-mailbox";
871 #mbox-cells = <1>;
872 ti,mbox-num-users = <4>;
873 ti,mbox-num-fifos = <16>;
874 interrupt-parent = <&main_navss_intr>;
879 compatible = "ti,am654-mailbox";
881 #mbox-cells = <1>;
882 ti,mbox-num-users = <4>;
883 ti,mbox-num-fifos = <16>;
884 interrupt-parent = <&main_navss_intr>;
889 compatible = "ti,am654-mailbox";
891 #mbox-cells = <1>;
892 ti,mbox-num-users = <4>;
893 ti,mbox-num-fifos = <16>;
894 interrupt-parent = <&main_navss_intr>;
899 compatible = "ti,am654-mailbox";
901 #mbox-cells = <1>;
902 ti,mbox-num-users = <4>;
903 ti,mbox-num-fifos = <16>;
904 interrupt-parent = <&main_navss_intr>;
909 compatible = "ti,am654-mailbox";
911 #mbox-cells = <1>;
912 ti,mbox-num-users = <4>;
913 ti,mbox-num-fifos = <16>;
914 interrupt-parent = <&main_navss_intr>;
919 compatible = "ti,am654-mailbox";
921 #mbox-cells = <1>;
922 ti,mbox-num-users = <4>;
923 ti,mbox-num-fifos = <16>;
924 interrupt-parent = <&main_navss_intr>;
929 compatible = "ti,am654-mailbox";
931 #mbox-cells = <1>;
932 ti,mbox-num-users = <4>;
933 ti,mbox-num-fifos = <16>;
934 interrupt-parent = <&main_navss_intr>;
939 compatible = "ti,am654-mailbox";
941 #mbox-cells = <1>;
942 ti,mbox-num-users = <4>;
943 ti,mbox-num-fifos = <16>;
944 interrupt-parent = <&main_navss_intr>;
949 compatible = "ti,am654-mailbox";
951 #mbox-cells = <1>;
952 ti,mbox-num-users = <4>;
953 ti,mbox-num-fifos = <16>;
954 interrupt-parent = <&main_navss_intr>;
959 compatible = "ti,am654-mailbox";
961 #mbox-cells = <1>;
962 ti,mbox-num-users = <4>;
963 ti,mbox-num-fifos = <16>;
964 interrupt-parent = <&main_navss_intr>;
969 compatible = "ti,am654-mailbox";
971 #mbox-cells = <1>;
972 ti,mbox-num-users = <4>;
973 ti,mbox-num-fifos = <16>;
974 interrupt-parent = <&main_navss_intr>;
979 compatible = "ti,am654-mailbox";
981 #mbox-cells = <1>;
982 ti,mbox-num-users = <4>;
983 ti,mbox-num-fifos = <16>;
984 interrupt-parent = <&main_navss_intr>;
989 compatible = "ti,am654-mailbox";
991 #mbox-cells = <1>;
992 ti,mbox-num-users = <4>;
993 ti,mbox-num-fifos = <16>;
994 interrupt-parent = <&main_navss_intr>;
999 compatible = "ti,am654-mailbox";
1001 #mbox-cells = <1>;
1002 ti,mbox-num-users = <4>;
1003 ti,mbox-num-fifos = <16>;
1004 interrupt-parent = <&main_navss_intr>;
1009 compatible = "ti,am654-mailbox";
1011 #mbox-cells = <1>;
1012 ti,mbox-num-users = <4>;
1013 ti,mbox-num-fifos = <16>;
1014 interrupt-parent = <&main_navss_intr>;
1019 compatible = "ti,am654-mailbox";
1021 #mbox-cells = <1>;
1022 ti,mbox-num-users = <4>;
1023 ti,mbox-num-fifos = <16>;
1024 interrupt-parent = <&main_navss_intr>;
1029 compatible = "ti,am654-mailbox";
1031 #mbox-cells = <1>;
1032 ti,mbox-num-users = <4>;
1033 ti,mbox-num-fifos = <16>;
1034 interrupt-parent = <&main_navss_intr>;
1039 compatible = "ti,am654-mailbox";
1041 #mbox-cells = <1>;
1042 ti,mbox-num-users = <4>;
1043 ti,mbox-num-fifos = <16>;
1044 interrupt-parent = <&main_navss_intr>;
1049 compatible = "ti,am654-mailbox";
1051 #mbox-cells = <1>;
1052 ti,mbox-num-users = <4>;
1053 ti,mbox-num-fifos = <16>;
1054 interrupt-parent = <&main_navss_intr>;
1059 compatible = "ti,am654-mailbox";
1061 #mbox-cells = <1>;
1062 ti,mbox-num-users = <4>;
1063 ti,mbox-num-fifos = <16>;
1064 interrupt-parent = <&main_navss_intr>;
1069 compatible = "ti,am654-navss-ringacc";
1075 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
1076 ti,num-rings = <1024>;
1077 ti,sci-rm-range-gp-rings = <0x1>;
1079 ti,sci-dev-id = <259>;
1080 msi-parent = <&main_udmass_inta>;
1083 main_udmap: dma-controller@31150000 {
1084 compatible = "ti,j721e-navss-main-udmap";
1091 reg-names = "gcfg", "rchanrt", "tchanrt",
1093 msi-parent = <&main_udmass_inta>;
1094 #dma-cells = <1>;
1097 ti,sci-dev-id = <263>;
1100 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1103 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1106 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1109 main_bcdma_csi: dma-controller@311a0000 {
1110 compatible = "ti,j721s2-dmss-bcdma-csi";
1115 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
1116 msi-parent = <&main_udmass_inta>;
1117 #dma-cells = <3>;
1119 ti,sci-dev-id = <225>;
1120 ti,sci-rm-range-rchan = <0x21>;
1121 ti,sci-rm-range-tchan = <0x22>;
1125 compatible = "ti,j721e-cpts";
1127 reg-names = "cpts";
1129 clock-names = "cpts";
1130 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
1131 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
1132 interrupts-extended = <&main_navss_intr 391>;
1133 interrupt-names = "cpts";
1134 ti,cpts-periodic-outputs = <6>;
1135 ti,cpts-ext-ts-inputs = <8>;
1140 compatible = "ti,j721e-cpsw-nuss";
1142 reg-names = "cpsw_nuss";
1144 #address-cells = <2>;
1145 #size-cells = <2>;
1146 dma-coherent;
1148 clock-names = "fck";
1149 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
1160 dma-names = "tx0", "tx1", "tx2", "tx3",
1166 ethernet-ports {
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1172 ti,mac-only;
1180 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1185 clock-names = "fck";
1191 compatible = "ti,am65-cpts";
1194 clock-names = "cpts";
1195 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1196 interrupt-names = "cpts";
1197 ti,cpts-ext-ts-inputs = <4>;
1198 ti,cpts-periodic-outputs = <2>;
1202 usbss0: cdns-usb@4104000 {
1203 compatible = "ti,j721e-usb";
1206 clock-names = "ref", "lpm";
1207 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
1208 assigned-clock-parents = <&k3_clks 360 17>;
1209 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
1210 #address-cells = <2>;
1211 #size-cells = <2>;
1213 dma-coherent;
1222 reg-names = "otg", "xhci", "dev";
1226 interrupt-names = "host", "peripheral", "otg";
1227 maximum-speed = "super-speed";
1233 compatible = "ti,j721e-csi2rx-shim";
1236 #address-cells = <2>;
1237 #size-cells = <2>;
1239 dma-names = "rx0";
1240 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
1243 cdns_csi2rx0: csi-bridge@4504000 {
1244 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1248 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1251 phy-names = "dphy";
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1286 compatible = "ti,j721e-csi2rx-shim";
1289 #address-cells = <2>;
1290 #size-cells = <2>;
1292 dma-names = "rx0";
1293 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
1296 cdns_csi2rx1: csi-bridge@4514000 {
1297 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1301 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1304 phy-names = "dphy";
1307 #address-cells = <1>;
1308 #size-cells = <0>;
1339 compatible = "cdns,dphy-rx";
1341 #phy-cells = <0>;
1342 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1347 compatible = "cdns,dphy-rx";
1349 #phy-cells = <0>;
1350 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1355 compatible = "ti,j721s2-wiz-10g";
1356 #address-cells = <1>;
1357 #size-cells = <1>;
1358 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
1360 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1361 num-lanes = <4>;
1362 #reset-cells = <1>;
1363 #clock-cells = <1>;
1366 assigned-clocks = <&k3_clks 365 3>;
1367 assigned-clock-parents = <&k3_clks 365 7>;
1370 compatible = "ti,j721e-serdes-10g";
1372 reg-names = "torrent_phy";
1374 reset-names = "torrent_reset";
1377 clock-names = "refclk", "phy_en_refclk";
1378 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1381 assigned-clock-parents = <&k3_clks 365 3>,
1384 #address-cells = <1>;
1385 #size-cells = <0>;
1386 #clock-cells = <1>;
1393 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
1398 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1399 interrupt-names = "link_state";
1402 ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
1403 max-link-speed = <3>;
1404 num-lanes = <4>;
1405 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
1407 clock-names = "fck";
1408 #address-cells = <3>;
1409 #size-cells = <2>;
1410 bus-range = <0x0 0xff>;
1411 vendor-id = <0x104c>;
1412 device-id = <0xb013>;
1413 msi-map = <0x0 &gic_its 0x0 0x10000>;
1414 dma-coherent;
1417 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1418 #interrupt-cells = <1>;
1419 interrupt-map-mask = <0 0 0 7>;
1420 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1427 pcie1_intc: interrupt-controller {
1428 interrupt-controller;
1429 #interrupt-cells = <1>;
1430 interrupt-parent = <&gic500>;
1439 reg-names = "m_can", "message_ram";
1440 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1442 clock-names = "hclk", "cclk";
1445 interrupt-names = "int0", "int1";
1446 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1454 reg-names = "m_can", "message_ram";
1455 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1457 clock-names = "hclk", "cclk";
1460 interrupt-names = "int0", "int1";
1461 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1469 reg-names = "m_can", "message_ram";
1470 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1472 clock-names = "hclk", "cclk";
1475 interrupt-names = "int0", "int1";
1476 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1484 reg-names = "m_can", "message_ram";
1485 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1487 clock-names = "hclk", "cclk";
1490 interrupt-names = "int0", "int1";
1491 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1499 reg-names = "m_can", "message_ram";
1500 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
1502 clock-names = "hclk", "cclk";
1505 interrupt-names = "int0", "int1";
1506 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1514 reg-names = "m_can", "message_ram";
1515 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
1517 clock-names = "hclk", "cclk";
1520 interrupt-names = "int0", "int1";
1521 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1529 reg-names = "m_can", "message_ram";
1530 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1532 clock-names = "hclk", "cclk";
1535 interrupt-names = "int0", "int1";
1536 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1544 reg-names = "m_can", "message_ram";
1545 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1547 clock-names = "hclk", "cclk";
1550 interrupt-names = "int0", "int1";
1551 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1559 reg-names = "m_can", "message_ram";
1560 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1562 clock-names = "hclk", "cclk";
1565 interrupt-names = "int0", "int1";
1566 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1574 reg-names = "m_can", "message_ram";
1575 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1577 clock-names = "hclk", "cclk";
1580 interrupt-names = "int0", "int1";
1581 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1589 reg-names = "m_can", "message_ram";
1590 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1592 clock-names = "hclk", "cclk";
1595 interrupt-names = "int0", "int1";
1596 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1604 reg-names = "m_can", "message_ram";
1605 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1607 clock-names = "hclk", "cclk";
1610 interrupt-names = "int0", "int1";
1611 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1619 reg-names = "m_can", "message_ram";
1620 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
1622 clock-names = "hclk", "cclk";
1625 interrupt-names = "int0", "int1";
1626 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1634 reg-names = "m_can", "message_ram";
1635 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
1637 clock-names = "hclk", "cclk";
1640 interrupt-names = "int0", "int1";
1641 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1649 reg-names = "m_can", "message_ram";
1650 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
1652 clock-names = "hclk", "cclk";
1655 interrupt-names = "int0", "int1";
1656 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1664 reg-names = "m_can", "message_ram";
1665 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
1667 clock-names = "hclk", "cclk";
1670 interrupt-names = "int0", "int1";
1671 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1679 reg-names = "m_can", "message_ram";
1680 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
1682 clock-names = "hclk", "cclk";
1685 interrupt-names = "int0", "int1";
1686 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1694 reg-names = "m_can", "message_ram";
1695 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
1697 clock-names = "hclk", "cclk";
1700 interrupt-names = "int0", "int1";
1701 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1706 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1709 #address-cells = <1>;
1710 #size-cells = <0>;
1711 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
1717 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1720 #address-cells = <1>;
1721 #size-cells = <0>;
1722 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
1728 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1731 #address-cells = <1>;
1732 #size-cells = <0>;
1733 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
1739 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1742 #address-cells = <1>;
1743 #size-cells = <0>;
1744 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
1750 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1753 #address-cells = <1>;
1754 #size-cells = <0>;
1755 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
1761 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1764 #address-cells = <1>;
1765 #size-cells = <0>;
1766 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
1772 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1775 #address-cells = <1>;
1776 #size-cells = <0>;
1777 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
1783 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1786 #address-cells = <1>;
1787 #size-cells = <0>;
1788 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
1794 compatible = "ti,j721e-dss";
1812 reg-names = "common_m", "common_s0",
1823 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1824 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
1829 interrupt-names = "common_m",
1840 compatible = "ti,j721s2-r5fss";
1841 ti,cluster-mode = <1>;
1842 #address-cells = <1>;
1843 #size-cells = <1>;
1846 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1849 compatible = "ti,j721s2-r5f";
1852 reg-names = "atcm", "btcm";
1854 ti,sci-dev-id = <279>;
1855 ti,sci-proc-ids = <0x06 0xff>;
1857 firmware-name = "j721s2-main-r5f0_0-fw";
1858 ti,atcm-enable = <1>;
1859 ti,btcm-enable = <1>;
1864 compatible = "ti,j721s2-r5f";
1867 reg-names = "atcm", "btcm";
1869 ti,sci-dev-id = <280>;
1870 ti,sci-proc-ids = <0x07 0xff>;
1872 firmware-name = "j721s2-main-r5f0_1-fw";
1873 ti,atcm-enable = <1>;
1874 ti,btcm-enable = <1>;
1880 compatible = "ti,j721s2-r5fss";
1881 ti,cluster-mode = <1>;
1882 #address-cells = <1>;
1883 #size-cells = <1>;
1886 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1889 compatible = "ti,j721s2-r5f";
1892 reg-names = "atcm", "btcm";
1894 ti,sci-dev-id = <281>;
1895 ti,sci-proc-ids = <0x08 0xff>;
1897 firmware-name = "j721s2-main-r5f1_0-fw";
1898 ti,atcm-enable = <1>;
1899 ti,btcm-enable = <1>;
1904 compatible = "ti,j721s2-r5f";
1907 reg-names = "atcm", "btcm";
1909 ti,sci-dev-id = <282>;
1910 ti,sci-proc-ids = <0x09 0xff>;
1912 firmware-name = "j721s2-main-r5f1_1-fw";
1913 ti,atcm-enable = <1>;
1914 ti,btcm-enable = <1>;
1920 compatible = "ti,j721s2-c71-dsp";
1923 reg-names = "l2sram", "l1dram";
1925 ti,sci-dev-id = <8>;
1926 ti,sci-proc-ids = <0x30 0xff>;
1928 firmware-name = "j721s2-c71_0-fw";
1933 compatible = "ti,j721s2-c71-dsp";
1936 reg-names = "l2sram", "l1dram";
1938 ti,sci-dev-id = <11>;
1939 ti,sci-proc-ids = <0x31 0xff>;
1941 firmware-name = "j721s2-c71_1-fw";
1946 compatible = "ti,j721e-esm";
1948 ti,esm-pins = <688>, <689>;
1949 bootph-pre-ram;
1953 compatible = "ti,j7-rti-wdt";
1956 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1957 assigned-clocks = <&k3_clks 286 1>;
1958 assigned-clock-parents = <&k3_clks 286 5>;
1962 compatible = "ti,j7-rti-wdt";
1965 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
1966 assigned-clocks = <&k3_clks 287 1>;
1967 assigned-clock-parents = <&k3_clks 287 5>;
1976 compatible = "ti,j7-rti-wdt";
1979 power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
1980 assigned-clocks = <&k3_clks 290 1>;
1981 assigned-clock-parents = <&k3_clks 290 5>;
1987 compatible = "ti,j7-rti-wdt";
1990 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1991 assigned-clocks = <&k3_clks 288 1>;
1992 assigned-clock-parents = <&k3_clks 288 5>;
1998 compatible = "ti,j7-rti-wdt";
2001 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
2002 assigned-clocks = <&k3_clks 289 1>;
2003 assigned-clock-parents = <&k3_clks 289 5>;
2009 compatible = "ti,j7-rti-wdt";
2012 power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
2013 assigned-clocks = <&k3_clks 291 1>;
2014 assigned-clock-parents = <&k3_clks 291 5>;
2020 compatible = "ti,j7-rti-wdt";
2023 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
2024 assigned-clocks = <&k3_clks 292 1>;
2025 assigned-clock-parents = <&k3_clks 292 5>;
2031 compatible = "ti,j7-rti-wdt";
2034 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
2035 assigned-clocks = <&k3_clks 293 1>;
2036 assigned-clock-parents = <&k3_clks 293 5>;
2042 compatible = "ti,j7-rti-wdt";
2045 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
2046 assigned-clocks = <&k3_clks 294 1>;
2047 assigned-clock-parents = <&k3_clks 294 5>;