Lines Matching +full:assigned +full:- +full:clock +full:- +full:parents
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
20 cmn_refclk1: clock-cmnrefclk1 {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <0>;
29 compatible = "mmio-sram";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 atf-sram@0 {
40 scm_conf: scm-conf@100000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
43 #address-cells = <1>;
44 #size-cells = <1>;
47 serdes_ln_ctrl: mux-controller@4080 {
48 compatible = "reg-mux";
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
57 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
66 compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
67 ti,qsgmii-main-ports = <2>, <2>;
69 #phy-cells = <1>;
72 usb_serdes_mux: mux-controller@4000 {
73 compatible = "reg-mux";
75 #mux-control-cells = <1>;
76 mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */
80 ehrpwm_tbclk: clock-controller@4140 {
81 compatible = "ti,am654-ehrpwm-tbclk";
83 #clock-cells = <1>;
88 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
89 #pwm-cells = <3>;
91 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
93 clock-names = "tbclk", "fck";
98 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
99 #pwm-cells = <3>;
101 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
103 clock-names = "tbclk", "fck";
108 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
109 #pwm-cells = <3>;
111 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
113 clock-names = "tbclk", "fck";
118 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
119 #pwm-cells = <3>;
121 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
123 clock-names = "tbclk", "fck";
128 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
129 #pwm-cells = <3>;
131 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
133 clock-names = "tbclk", "fck";
138 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
139 #pwm-cells = <3>;
141 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
143 clock-names = "tbclk", "fck";
147 gic500: interrupt-controller@1800000 {
148 compatible = "arm,gic-v3";
149 #address-cells = <2>;
150 #size-cells = <2>;
152 #interrupt-cells = <3>;
153 interrupt-controller;
163 gic_its: msi-controller@1820000 {
164 compatible = "arm,gic-v3-its";
166 socionext,synquacer-pre-its = <0x1000000 0x400000>;
167 msi-controller;
168 #msi-cells = <1>;
172 main_gpio_intr: interrupt-controller@a00000 {
173 compatible = "ti,sci-intr";
175 ti,intr-trigger-type = <1>;
176 interrupt-controller;
177 interrupt-parent = <&gic500>;
178 #interrupt-cells = <1>;
180 ti,sci-dev-id = <131>;
181 ti,interrupt-ranges = <8 392 56>;
185 compatible = "simple-bus";
186 #address-cells = <2>;
187 #size-cells = <2>;
189 dma-coherent;
190 dma-ranges;
192 ti,sci-dev-id = <199>;
194 main_navss_intr: interrupt-controller@310e0000 {
195 compatible = "ti,sci-intr";
197 ti,intr-trigger-type = <4>;
198 interrupt-controller;
199 interrupt-parent = <&gic500>;
200 #interrupt-cells = <1>;
202 ti,sci-dev-id = <213>;
203 ti,interrupt-ranges = <0 64 64>,
208 main_udmass_inta: interrupt-controller@33d00000 {
209 compatible = "ti,sci-inta";
211 interrupt-controller;
212 interrupt-parent = <&main_navss_intr>;
213 msi-controller;
214 #interrupt-cells = <0>;
216 ti,sci-dev-id = <209>;
217 ti,interrupt-ranges = <0 0 256>;
221 compatible = "ti,am654-secure-proxy";
222 #mbox-cells = <1>;
223 reg-names = "target_data", "rt", "scfg";
227 interrupt-names = "rx_011";
229 bootph-all;
233 compatible = "arm,smmu-v3";
235 interrupt-parent = <&gic500>;
238 interrupt-names = "eventq", "gerror";
239 #iommu-cells = <1>;
243 compatible = "ti,am654-hwspinlock";
245 #hwlock-cells = <1>;
249 compatible = "ti,am654-mailbox";
251 #mbox-cells = <1>;
252 ti,mbox-num-users = <4>;
253 ti,mbox-num-fifos = <16>;
254 interrupt-parent = <&main_navss_intr>;
259 compatible = "ti,am654-mailbox";
261 #mbox-cells = <1>;
262 ti,mbox-num-users = <4>;
263 ti,mbox-num-fifos = <16>;
264 interrupt-parent = <&main_navss_intr>;
269 compatible = "ti,am654-mailbox";
271 #mbox-cells = <1>;
272 ti,mbox-num-users = <4>;
273 ti,mbox-num-fifos = <16>;
274 interrupt-parent = <&main_navss_intr>;
279 compatible = "ti,am654-mailbox";
281 #mbox-cells = <1>;
282 ti,mbox-num-users = <4>;
283 ti,mbox-num-fifos = <16>;
284 interrupt-parent = <&main_navss_intr>;
289 compatible = "ti,am654-mailbox";
291 #mbox-cells = <1>;
292 ti,mbox-num-users = <4>;
293 ti,mbox-num-fifos = <16>;
294 interrupt-parent = <&main_navss_intr>;
299 compatible = "ti,am654-mailbox";
301 #mbox-cells = <1>;
302 ti,mbox-num-users = <4>;
303 ti,mbox-num-fifos = <16>;
304 interrupt-parent = <&main_navss_intr>;
309 compatible = "ti,am654-mailbox";
311 #mbox-cells = <1>;
312 ti,mbox-num-users = <4>;
313 ti,mbox-num-fifos = <16>;
314 interrupt-parent = <&main_navss_intr>;
319 compatible = "ti,am654-mailbox";
321 #mbox-cells = <1>;
322 ti,mbox-num-users = <4>;
323 ti,mbox-num-fifos = <16>;
324 interrupt-parent = <&main_navss_intr>;
329 compatible = "ti,am654-mailbox";
331 #mbox-cells = <1>;
332 ti,mbox-num-users = <4>;
333 ti,mbox-num-fifos = <16>;
334 interrupt-parent = <&main_navss_intr>;
339 compatible = "ti,am654-mailbox";
341 #mbox-cells = <1>;
342 ti,mbox-num-users = <4>;
343 ti,mbox-num-fifos = <16>;
344 interrupt-parent = <&main_navss_intr>;
349 compatible = "ti,am654-mailbox";
351 #mbox-cells = <1>;
352 ti,mbox-num-users = <4>;
353 ti,mbox-num-fifos = <16>;
354 interrupt-parent = <&main_navss_intr>;
359 compatible = "ti,am654-mailbox";
361 #mbox-cells = <1>;
362 ti,mbox-num-users = <4>;
363 ti,mbox-num-fifos = <16>;
364 interrupt-parent = <&main_navss_intr>;
369 compatible = "ti,am654-navss-ringacc";
375 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
376 ti,num-rings = <1024>;
377 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
379 ti,sci-dev-id = <211>;
380 msi-parent = <&main_udmass_inta>;
383 main_udmap: dma-controller@31150000 {
384 compatible = "ti,j721e-navss-main-udmap";
391 reg-names = "gcfg", "rchanrt", "tchanrt",
393 msi-parent = <&main_udmass_inta>;
394 #dma-cells = <1>;
397 ti,sci-dev-id = <212>;
400 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
403 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
406 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
410 compatible = "ti,j721e-cpts";
412 reg-names = "cpts";
414 clock-names = "cpts";
415 interrupts-extended = <&main_navss_intr 391>;
416 interrupt-names = "cpts";
417 ti,cpts-periodic-outputs = <6>;
418 ti,cpts-ext-ts-inputs = <8>;
423 compatible = "ti,j721e-cpswxg-nuss";
424 #address-cells = <2>;
425 #size-cells = <2>;
427 reg-names = "cpsw_nuss";
430 clock-names = "fck";
431 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
442 dma-names = "tx0", "tx1", "tx2", "tx3",
448 ethernet-ports {
449 #address-cells = <1>;
450 #size-cells = <0>;
453 ti,mac-only;
460 ti,mac-only;
467 ti,mac-only;
474 ti,mac-only;
481 ti,mac-only;
488 ti,mac-only;
495 ti,mac-only;
502 ti,mac-only;
509 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
511 #address-cells = <1>;
512 #size-cells = <0>;
514 clock-names = "fck";
520 compatible = "ti,j721e-cpts";
523 clock-names = "cpts";
524 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
525 interrupt-names = "cpts";
526 ti,cpts-ext-ts-inputs = <4>;
527 ti,cpts-periodic-outputs = <2>;
532 compatible = "ti,j721e-sa2ul";
534 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
535 #address-cells = <2>;
536 #size-cells = <2>;
541 dma-names = "tx", "rx1", "rx2";
544 compatible = "inside-secure,safexcel-eip76";
551 compatible = "pinctrl-single";
554 #pinctrl-cells = <1>;
555 pinctrl-single,register-width = <32>;
556 pinctrl-single,function-mask = <0xffffffff>;
561 compatible = "pinctrl-single";
563 #pinctrl-cells = <1>;
564 pinctrl-single,register-width = <32>;
565 pinctrl-single,function-mask = <0x00000007>;
570 compatible = "pinctrl-single";
572 #pinctrl-cells = <1>;
573 pinctrl-single,register-width = <32>;
574 pinctrl-single,function-mask = <0x0000001f>;
578 compatible = "ti,j721e-csi2rx-shim";
581 #address-cells = <2>;
582 #size-cells = <2>;
584 dma-names = "rx0";
585 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
588 cdns_csi2rx0: csi-bridge@4504000 {
589 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
593 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
596 phy-names = "dphy";
599 #address-cells = <1>;
600 #size-cells = <0>;
631 compatible = "ti,j721e-csi2rx-shim";
634 #address-cells = <2>;
635 #size-cells = <2>;
637 dma-names = "rx0";
638 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
641 cdns_csi2rx1: csi-bridge@4514000 {
642 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
646 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
649 phy-names = "dphy";
652 #address-cells = <1>;
653 #size-cells = <0>;
684 compatible = "cdns,dphy-rx";
686 #phy-cells = <0>;
687 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
692 compatible = "cdns,dphy-rx";
694 #phy-cells = <0>;
695 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
700 compatible = "ti,j721e-wiz-16g";
701 #address-cells = <1>;
702 #size-cells = <1>;
703 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
705 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
706 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
707 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
708 num-lanes = <2>;
709 #reset-cells = <1>;
712 wiz0_pll0_refclk: pll0-refclk {
714 #clock-cells = <0>;
715 assigned-clocks = <&wiz0_pll0_refclk>;
716 assigned-clock-parents = <&k3_clks 292 11>;
719 wiz0_pll1_refclk: pll1-refclk {
721 #clock-cells = <0>;
722 assigned-clocks = <&wiz0_pll1_refclk>;
723 assigned-clock-parents = <&k3_clks 292 0>;
726 wiz0_refclk_dig: refclk-dig {
728 #clock-cells = <0>;
729 assigned-clocks = <&wiz0_refclk_dig>;
730 assigned-clock-parents = <&k3_clks 292 11>;
733 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
735 #clock-cells = <0>;
738 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
740 #clock-cells = <0>;
744 compatible = "ti,sierra-phy-t0";
745 reg-names = "serdes";
747 #address-cells = <1>;
748 #size-cells = <0>;
749 #clock-cells = <1>;
751 reset-names = "sierra_reset";
754 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
760 compatible = "ti,j721e-wiz-16g";
761 #address-cells = <1>;
762 #size-cells = <1>;
763 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
765 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
766 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
767 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
768 num-lanes = <2>;
769 #reset-cells = <1>;
772 wiz1_pll0_refclk: pll0-refclk {
774 #clock-cells = <0>;
775 assigned-clocks = <&wiz1_pll0_refclk>;
776 assigned-clock-parents = <&k3_clks 293 13>;
779 wiz1_pll1_refclk: pll1-refclk {
781 #clock-cells = <0>;
782 assigned-clocks = <&wiz1_pll1_refclk>;
783 assigned-clock-parents = <&k3_clks 293 0>;
786 wiz1_refclk_dig: refclk-dig {
788 #clock-cells = <0>;
789 assigned-clocks = <&wiz1_refclk_dig>;
790 assigned-clock-parents = <&k3_clks 293 13>;
793 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
795 #clock-cells = <0>;
798 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
800 #clock-cells = <0>;
804 compatible = "ti,sierra-phy-t0";
805 reg-names = "serdes";
807 #address-cells = <1>;
808 #size-cells = <0>;
809 #clock-cells = <1>;
811 reset-names = "sierra_reset";
814 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
820 compatible = "ti,j721e-wiz-16g";
821 #address-cells = <1>;
822 #size-cells = <1>;
823 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
825 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
826 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
827 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
828 num-lanes = <2>;
829 #reset-cells = <1>;
832 wiz2_pll0_refclk: pll0-refclk {
834 #clock-cells = <0>;
835 assigned-clocks = <&wiz2_pll0_refclk>;
836 assigned-clock-parents = <&k3_clks 294 11>;
839 wiz2_pll1_refclk: pll1-refclk {
841 #clock-cells = <0>;
842 assigned-clocks = <&wiz2_pll1_refclk>;
843 assigned-clock-parents = <&k3_clks 294 0>;
846 wiz2_refclk_dig: refclk-dig {
848 #clock-cells = <0>;
849 assigned-clocks = <&wiz2_refclk_dig>;
850 assigned-clock-parents = <&k3_clks 294 11>;
853 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
855 #clock-cells = <0>;
858 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
860 #clock-cells = <0>;
864 compatible = "ti,sierra-phy-t0";
865 reg-names = "serdes";
867 #address-cells = <1>;
868 #size-cells = <0>;
869 #clock-cells = <1>;
871 reset-names = "sierra_reset";
874 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
880 compatible = "ti,j721e-wiz-16g";
881 #address-cells = <1>;
882 #size-cells = <1>;
883 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
885 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
886 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
887 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
888 num-lanes = <2>;
889 #reset-cells = <1>;
892 wiz3_pll0_refclk: pll0-refclk {
894 #clock-cells = <0>;
895 assigned-clocks = <&wiz3_pll0_refclk>;
896 assigned-clock-parents = <&k3_clks 295 9>;
899 wiz3_pll1_refclk: pll1-refclk {
901 #clock-cells = <0>;
902 assigned-clocks = <&wiz3_pll1_refclk>;
903 assigned-clock-parents = <&k3_clks 295 0>;
906 wiz3_refclk_dig: refclk-dig {
908 #clock-cells = <0>;
909 assigned-clocks = <&wiz3_refclk_dig>;
910 assigned-clock-parents = <&k3_clks 295 9>;
913 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
915 #clock-cells = <0>;
918 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
920 #clock-cells = <0>;
924 compatible = "ti,sierra-phy-t0";
925 reg-names = "serdes";
927 #address-cells = <1>;
928 #size-cells = <0>;
929 #clock-cells = <1>;
931 reset-names = "sierra_reset";
934 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
940 compatible = "ti,j721e-pcie-host";
945 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
946 interrupt-names = "link_state";
949 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
950 max-link-speed = <3>;
951 num-lanes = <2>;
952 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
954 clock-names = "fck";
955 #address-cells = <3>;
956 #size-cells = <2>;
957 bus-range = <0x0 0xff>;
958 vendor-id = <0x104c>;
959 device-id = <0xb00d>;
960 msi-map = <0x0 &gic_its 0x0 0x10000>;
961 dma-coherent;
964 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
969 compatible = "ti,j721e-pcie-host";
974 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
975 interrupt-names = "link_state";
978 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
979 max-link-speed = <3>;
980 num-lanes = <2>;
981 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
983 clock-names = "fck";
984 #address-cells = <3>;
985 #size-cells = <2>;
986 bus-range = <0x0 0xff>;
987 vendor-id = <0x104c>;
988 device-id = <0xb00d>;
989 msi-map = <0x0 &gic_its 0x10000 0x10000>;
990 dma-coherent;
993 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
998 compatible = "ti,j721e-pcie-host";
1003 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1004 interrupt-names = "link_state";
1007 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
1008 max-link-speed = <3>;
1009 num-lanes = <2>;
1010 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
1012 clock-names = "fck";
1013 #address-cells = <3>;
1014 #size-cells = <2>;
1015 bus-range = <0x0 0xff>;
1016 vendor-id = <0x104c>;
1017 device-id = <0xb00d>;
1018 msi-map = <0x0 &gic_its 0x20000 0x10000>;
1019 dma-coherent;
1022 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1027 compatible = "ti,j721e-pcie-host";
1032 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1033 interrupt-names = "link_state";
1036 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
1037 max-link-speed = <3>;
1038 num-lanes = <2>;
1039 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
1041 clock-names = "fck";
1042 #address-cells = <3>;
1043 #size-cells = <2>;
1044 bus-range = <0x0 0xff>;
1045 vendor-id = <0x104c>;
1046 device-id = <0xb00d>;
1047 msi-map = <0x0 &gic_its 0x30000 0x10000>;
1048 dma-coherent;
1051 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1056 compatible = "ti,am64-wiz-10g";
1057 #address-cells = <1>;
1058 #size-cells = <1>;
1059 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
1061 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1062 assigned-clocks = <&k3_clks 297 9>;
1063 assigned-clock-parents = <&k3_clks 297 10>;
1064 assigned-clock-rates = <19200000>;
1065 num-lanes = <4>;
1066 #reset-cells = <1>;
1067 #clock-cells = <1>;
1076 compatible = "ti,j721e-serdes-10g";
1079 reg-names = "torrent_phy", "dptx_phy";
1082 reset-names = "torrent_reset";
1084 clock-names = "refclk";
1085 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
1088 assigned-clock-parents = <&k3_clks 297 9>,
1091 #address-cells = <1>;
1092 #size-cells = <0>;
1097 compatible = "ti,am654-timer";
1101 clock-names = "fck";
1102 assigned-clocks = <&k3_clks 49 1>;
1103 assigned-clock-parents = <&k3_clks 49 2>;
1104 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1105 ti,timer-pwm;
1109 compatible = "ti,am654-timer";
1113 clock-names = "fck";
1114 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
1115 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
1116 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1117 ti,timer-pwm;
1121 compatible = "ti,am654-timer";
1125 clock-names = "fck";
1126 assigned-clocks = <&k3_clks 51 1>;
1127 assigned-clock-parents = <&k3_clks 51 2>;
1128 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
1129 ti,timer-pwm;
1133 compatible = "ti,am654-timer";
1137 clock-names = "fck";
1138 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1139 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
1140 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1141 ti,timer-pwm;
1145 compatible = "ti,am654-timer";
1149 clock-names = "fck";
1150 assigned-clocks = <&k3_clks 53 1>;
1151 assigned-clock-parents = <&k3_clks 53 2>;
1152 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1153 ti,timer-pwm;
1157 compatible = "ti,am654-timer";
1161 clock-names = "fck";
1162 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1163 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
1164 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1165 ti,timer-pwm;
1169 compatible = "ti,am654-timer";
1173 clock-names = "fck";
1174 assigned-clocks = <&k3_clks 55 1>;
1175 assigned-clock-parents = <&k3_clks 55 2>;
1176 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1177 ti,timer-pwm;
1181 compatible = "ti,am654-timer";
1185 clock-names = "fck";
1186 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1187 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
1188 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1189 ti,timer-pwm;
1193 compatible = "ti,am654-timer";
1197 clock-names = "fck";
1198 assigned-clocks = <&k3_clks 58 1>;
1199 assigned-clock-parents = <&k3_clks 58 2>;
1200 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1201 ti,timer-pwm;
1205 compatible = "ti,am654-timer";
1209 clock-names = "fck";
1210 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1211 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
1212 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1213 ti,timer-pwm;
1217 compatible = "ti,am654-timer";
1221 clock-names = "fck";
1222 assigned-clocks = <&k3_clks 60 1>;
1223 assigned-clock-parents = <&k3_clks 60 2>;
1224 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1225 ti,timer-pwm;
1229 compatible = "ti,am654-timer";
1233 clock-names = "fck";
1234 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1235 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
1236 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1237 ti,timer-pwm;
1241 compatible = "ti,am654-timer";
1245 clock-names = "fck";
1246 assigned-clocks = <&k3_clks 63 1>;
1247 assigned-clock-parents = <&k3_clks 63 2>;
1248 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1249 ti,timer-pwm;
1253 compatible = "ti,am654-timer";
1257 clock-names = "fck";
1258 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1259 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
1260 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1261 ti,timer-pwm;
1265 compatible = "ti,am654-timer";
1269 clock-names = "fck";
1270 assigned-clocks = <&k3_clks 65 1>;
1271 assigned-clock-parents = <&k3_clks 65 2>;
1272 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1273 ti,timer-pwm;
1277 compatible = "ti,am654-timer";
1281 clock-names = "fck";
1282 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1283 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
1284 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1285 ti,timer-pwm;
1289 compatible = "ti,am654-timer";
1293 clock-names = "fck";
1294 assigned-clocks = <&k3_clks 67 1>;
1295 assigned-clock-parents = <&k3_clks 67 2>;
1296 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1297 ti,timer-pwm;
1301 compatible = "ti,am654-timer";
1305 clock-names = "fck";
1306 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1307 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
1308 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1309 ti,timer-pwm;
1313 compatible = "ti,am654-timer";
1317 clock-names = "fck";
1318 assigned-clocks = <&k3_clks 69 1>;
1319 assigned-clock-parents = <&k3_clks 69 2>;
1320 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1321 ti,timer-pwm;
1325 compatible = "ti,am654-timer";
1329 clock-names = "fck";
1330 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1331 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
1332 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1333 ti,timer-pwm;
1337 compatible = "ti,j721e-uart", "ti,am654-uart";
1340 clock-frequency = <48000000>;
1341 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
1343 clock-names = "fclk";
1348 compatible = "ti,j721e-uart", "ti,am654-uart";
1351 clock-frequency = <48000000>;
1352 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1354 clock-names = "fclk";
1359 compatible = "ti,j721e-uart", "ti,am654-uart";
1362 clock-frequency = <48000000>;
1363 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
1365 clock-names = "fclk";
1370 compatible = "ti,j721e-uart", "ti,am654-uart";
1373 clock-frequency = <48000000>;
1374 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
1376 clock-names = "fclk";
1381 compatible = "ti,j721e-uart", "ti,am654-uart";
1384 clock-frequency = <48000000>;
1385 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
1387 clock-names = "fclk";
1392 compatible = "ti,j721e-uart", "ti,am654-uart";
1395 clock-frequency = <48000000>;
1396 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
1398 clock-names = "fclk";
1403 compatible = "ti,j721e-uart", "ti,am654-uart";
1406 clock-frequency = <48000000>;
1407 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
1409 clock-names = "fclk";
1414 compatible = "ti,j721e-uart", "ti,am654-uart";
1417 clock-frequency = <48000000>;
1418 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
1420 clock-names = "fclk";
1425 compatible = "ti,j721e-uart", "ti,am654-uart";
1428 clock-frequency = <48000000>;
1429 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
1431 clock-names = "fclk";
1436 compatible = "ti,j721e-uart", "ti,am654-uart";
1439 clock-frequency = <48000000>;
1440 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1442 clock-names = "fclk";
1447 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1449 gpio-controller;
1450 #gpio-cells = <2>;
1451 interrupt-parent = <&main_gpio_intr>;
1454 interrupt-controller;
1455 #interrupt-cells = <2>;
1457 ti,davinci-gpio-unbanked = <0>;
1458 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
1460 clock-names = "gpio";
1465 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1467 gpio-controller;
1468 #gpio-cells = <2>;
1469 interrupt-parent = <&main_gpio_intr>;
1471 interrupt-controller;
1472 #interrupt-cells = <2>;
1474 ti,davinci-gpio-unbanked = <0>;
1475 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
1477 clock-names = "gpio";
1482 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1484 gpio-controller;
1485 #gpio-cells = <2>;
1486 interrupt-parent = <&main_gpio_intr>;
1489 interrupt-controller;
1490 #interrupt-cells = <2>;
1492 ti,davinci-gpio-unbanked = <0>;
1493 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
1495 clock-names = "gpio";
1500 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1502 gpio-controller;
1503 #gpio-cells = <2>;
1504 interrupt-parent = <&main_gpio_intr>;
1506 interrupt-controller;
1507 #interrupt-cells = <2>;
1509 ti,davinci-gpio-unbanked = <0>;
1510 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1512 clock-names = "gpio";
1517 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1519 gpio-controller;
1520 #gpio-cells = <2>;
1521 interrupt-parent = <&main_gpio_intr>;
1524 interrupt-controller;
1525 #interrupt-cells = <2>;
1527 ti,davinci-gpio-unbanked = <0>;
1528 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1530 clock-names = "gpio";
1535 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1537 gpio-controller;
1538 #gpio-cells = <2>;
1539 interrupt-parent = <&main_gpio_intr>;
1541 interrupt-controller;
1542 #interrupt-cells = <2>;
1544 ti,davinci-gpio-unbanked = <0>;
1545 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1547 clock-names = "gpio";
1552 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1554 gpio-controller;
1555 #gpio-cells = <2>;
1556 interrupt-parent = <&main_gpio_intr>;
1559 interrupt-controller;
1560 #interrupt-cells = <2>;
1562 ti,davinci-gpio-unbanked = <0>;
1563 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1565 clock-names = "gpio";
1570 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1572 gpio-controller;
1573 #gpio-cells = <2>;
1574 interrupt-parent = <&main_gpio_intr>;
1576 interrupt-controller;
1577 #interrupt-cells = <2>;
1579 ti,davinci-gpio-unbanked = <0>;
1580 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1582 clock-names = "gpio";
1587 compatible = "ti,j721e-sdhci-8bit";
1590 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1591 clock-names = "clk_ahb", "clk_xin";
1593 assigned-clocks = <&k3_clks 91 1>;
1594 assigned-clock-parents = <&k3_clks 91 2>;
1595 bus-width = <8>;
1596 mmc-hs200-1_8v;
1597 mmc-ddr-1_8v;
1598 ti,otap-del-sel-legacy = <0x0>;
1599 ti,otap-del-sel-mmc-hs = <0x0>;
1600 ti,otap-del-sel-ddr52 = <0x5>;
1601 ti,otap-del-sel-hs200 = <0x6>;
1602 ti,otap-del-sel-hs400 = <0x0>;
1603 ti,itap-del-sel-legacy = <0x10>;
1604 ti,itap-del-sel-mmc-hs = <0xa>;
1605 ti,itap-del-sel-ddr52 = <0x3>;
1606 ti,trm-icp = <0x8>;
1607 dma-coherent;
1612 compatible = "ti,j721e-sdhci-4bit";
1615 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1616 clock-names = "clk_ahb", "clk_xin";
1618 assigned-clocks = <&k3_clks 92 0>;
1619 assigned-clock-parents = <&k3_clks 92 1>;
1620 ti,otap-del-sel-legacy = <0x0>;
1621 ti,otap-del-sel-sd-hs = <0x0>;
1622 ti,otap-del-sel-sdr12 = <0xf>;
1623 ti,otap-del-sel-sdr25 = <0xf>;
1624 ti,otap-del-sel-sdr50 = <0xc>;
1625 ti,otap-del-sel-ddr50 = <0xc>;
1626 ti,otap-del-sel-sdr104 = <0x5>;
1627 ti,itap-del-sel-legacy = <0x0>;
1628 ti,itap-del-sel-sd-hs = <0x0>;
1629 ti,itap-del-sel-sdr12 = <0x0>;
1630 ti,itap-del-sel-sdr25 = <0x0>;
1631 ti,itap-del-sel-ddr50 = <0x2>;
1632 ti,trm-icp = <0x8>;
1633 ti,clkbuf-sel = <0x7>;
1634 dma-coherent;
1635 sdhci-caps-mask = <0x2 0x0>;
1640 compatible = "ti,j721e-sdhci-4bit";
1643 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1644 clock-names = "clk_ahb", "clk_xin";
1646 assigned-clocks = <&k3_clks 93 0>;
1647 assigned-clock-parents = <&k3_clks 93 1>;
1648 ti,otap-del-sel-legacy = <0x0>;
1649 ti,otap-del-sel-sd-hs = <0x0>;
1650 ti,otap-del-sel-sdr12 = <0xf>;
1651 ti,otap-del-sel-sdr25 = <0xf>;
1652 ti,otap-del-sel-sdr50 = <0xc>;
1653 ti,otap-del-sel-ddr50 = <0xc>;
1654 ti,otap-del-sel-sdr104 = <0x5>;
1655 ti,itap-del-sel-legacy = <0x0>;
1656 ti,itap-del-sel-sd-hs = <0x0>;
1657 ti,itap-del-sel-sdr12 = <0x0>;
1658 ti,itap-del-sel-sdr25 = <0x0>;
1659 ti,itap-del-sel-ddr50 = <0x2>;
1660 ti,trm-icp = <0x8>;
1661 ti,clkbuf-sel = <0x7>;
1662 dma-coherent;
1663 sdhci-caps-mask = <0x2 0x0>;
1667 usbss0: cdns-usb@4104000 {
1668 compatible = "ti,j721e-usb";
1670 dma-coherent;
1671 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1673 clock-names = "ref", "lpm";
1674 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1675 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1676 #address-cells = <2>;
1677 #size-cells = <2>;
1685 reg-names = "otg", "xhci", "dev";
1689 interrupt-names = "host",
1692 maximum-speed = "super-speed";
1697 usbss1: cdns-usb@4114000 {
1698 compatible = "ti,j721e-usb";
1700 dma-coherent;
1701 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1703 clock-names = "ref", "lpm";
1704 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1705 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1706 #address-cells = <2>;
1707 #size-cells = <2>;
1715 reg-names = "otg", "xhci", "dev";
1719 interrupt-names = "host",
1722 maximum-speed = "super-speed";
1728 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1731 #address-cells = <1>;
1732 #size-cells = <0>;
1733 clock-names = "fck";
1735 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1740 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1743 #address-cells = <1>;
1744 #size-cells = <0>;
1745 clock-names = "fck";
1747 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1752 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1755 #address-cells = <1>;
1756 #size-cells = <0>;
1757 clock-names = "fck";
1759 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1764 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1767 #address-cells = <1>;
1768 #size-cells = <0>;
1769 clock-names = "fck";
1771 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1776 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1779 #address-cells = <1>;
1780 #size-cells = <0>;
1781 clock-names = "fck";
1783 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1788 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1791 #address-cells = <1>;
1792 #size-cells = <0>;
1793 clock-names = "fck";
1795 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1800 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1803 #address-cells = <1>;
1804 #size-cells = <0>;
1805 clock-names = "fck";
1807 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1811 ufs_wrapper: ufs-wrapper@4e80000 {
1812 compatible = "ti,j721e-ufs";
1814 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1816 assigned-clocks = <&k3_clks 277 1>;
1817 assigned-clock-parents = <&k3_clks 277 4>;
1819 #address-cells = <2>;
1820 #size-cells = <2>;
1823 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1826 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1828 clock-names = "core_clk", "phy_clk", "ref_clk";
1829 dma-coherent;
1833 mhdp: dp-bridge@a000000 {
1834 compatible = "ti,j721e-mhdp8546";
1841 reg-names = "mhdptx", "j721e-intg";
1845 interrupt-parent = <&gic500>;
1848 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1851 #address-cells = <1>;
1852 #size-cells = <0>;
1865 compatible = "ti,j721e-dss";
1888 reg-names = "common_m", "common_s0",
1900 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1902 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1908 interrupt-names = "common_m",
1918 compatible = "ti,am33xx-mcasp-audio";
1921 reg-names = "mpu","dat";
1924 interrupt-names = "tx", "rx";
1927 dma-names = "tx", "rx";
1930 clock-names = "fck";
1931 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1936 compatible = "ti,am33xx-mcasp-audio";
1939 reg-names = "mpu","dat";
1942 interrupt-names = "tx", "rx";
1945 dma-names = "tx", "rx";
1948 clock-names = "fck";
1949 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1954 compatible = "ti,am33xx-mcasp-audio";
1957 reg-names = "mpu","dat";
1960 interrupt-names = "tx", "rx";
1963 dma-names = "tx", "rx";
1966 clock-names = "fck";
1967 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1972 compatible = "ti,am33xx-mcasp-audio";
1975 reg-names = "mpu","dat";
1978 interrupt-names = "tx", "rx";
1981 dma-names = "tx", "rx";
1984 clock-names = "fck";
1985 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1990 compatible = "ti,am33xx-mcasp-audio";
1993 reg-names = "mpu","dat";
1996 interrupt-names = "tx", "rx";
1999 dma-names = "tx", "rx";
2002 clock-names = "fck";
2003 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
2008 compatible = "ti,am33xx-mcasp-audio";
2011 reg-names = "mpu","dat";
2014 interrupt-names = "tx", "rx";
2017 dma-names = "tx", "rx";
2020 clock-names = "fck";
2021 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
2026 compatible = "ti,am33xx-mcasp-audio";
2029 reg-names = "mpu","dat";
2032 interrupt-names = "tx", "rx";
2035 dma-names = "tx", "rx";
2038 clock-names = "fck";
2039 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
2044 compatible = "ti,am33xx-mcasp-audio";
2047 reg-names = "mpu","dat";
2050 interrupt-names = "tx", "rx";
2053 dma-names = "tx", "rx";
2056 clock-names = "fck";
2057 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
2062 compatible = "ti,am33xx-mcasp-audio";
2065 reg-names = "mpu","dat";
2068 interrupt-names = "tx", "rx";
2071 dma-names = "tx", "rx";
2074 clock-names = "fck";
2075 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
2080 compatible = "ti,am33xx-mcasp-audio";
2083 reg-names = "mpu","dat";
2086 interrupt-names = "tx", "rx";
2089 dma-names = "tx", "rx";
2092 clock-names = "fck";
2093 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
2098 compatible = "ti,am33xx-mcasp-audio";
2101 reg-names = "mpu","dat";
2104 interrupt-names = "tx", "rx";
2107 dma-names = "tx", "rx";
2110 clock-names = "fck";
2111 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
2116 compatible = "ti,am33xx-mcasp-audio";
2119 reg-names = "mpu","dat";
2122 interrupt-names = "tx", "rx";
2125 dma-names = "tx", "rx";
2128 clock-names = "fck";
2129 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
2134 compatible = "ti,j7-rti-wdt";
2137 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
2138 assigned-clocks = <&k3_clks 252 1>;
2139 assigned-clock-parents = <&k3_clks 252 5>;
2143 compatible = "ti,j7-rti-wdt";
2146 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
2147 assigned-clocks = <&k3_clks 253 1>;
2148 assigned-clock-parents = <&k3_clks 253 5>;
2152 compatible = "ti,j721e-r5fss";
2153 ti,cluster-mode = <1>;
2154 #address-cells = <1>;
2155 #size-cells = <1>;
2158 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
2161 compatible = "ti,j721e-r5f";
2164 reg-names = "atcm", "btcm";
2166 ti,sci-dev-id = <245>;
2167 ti,sci-proc-ids = <0x06 0xff>;
2169 firmware-name = "j7-main-r5f0_0-fw";
2170 ti,atcm-enable = <1>;
2171 ti,btcm-enable = <1>;
2176 compatible = "ti,j721e-r5f";
2179 reg-names = "atcm", "btcm";
2181 ti,sci-dev-id = <246>;
2182 ti,sci-proc-ids = <0x07 0xff>;
2184 firmware-name = "j7-main-r5f0_1-fw";
2185 ti,atcm-enable = <1>;
2186 ti,btcm-enable = <1>;
2192 compatible = "ti,j721e-r5fss";
2193 ti,cluster-mode = <1>;
2194 #address-cells = <1>;
2195 #size-cells = <1>;
2198 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
2201 compatible = "ti,j721e-r5f";
2204 reg-names = "atcm", "btcm";
2206 ti,sci-dev-id = <247>;
2207 ti,sci-proc-ids = <0x08 0xff>;
2209 firmware-name = "j7-main-r5f1_0-fw";
2210 ti,atcm-enable = <1>;
2211 ti,btcm-enable = <1>;
2216 compatible = "ti,j721e-r5f";
2219 reg-names = "atcm", "btcm";
2221 ti,sci-dev-id = <248>;
2222 ti,sci-proc-ids = <0x09 0xff>;
2224 firmware-name = "j7-main-r5f1_1-fw";
2225 ti,atcm-enable = <1>;
2226 ti,btcm-enable = <1>;
2232 compatible = "ti,j721e-c66-dsp";
2236 reg-names = "l2sram", "l1pram", "l1dram";
2238 ti,sci-dev-id = <142>;
2239 ti,sci-proc-ids = <0x03 0xff>;
2241 firmware-name = "j7-c66_0-fw";
2246 compatible = "ti,j721e-c66-dsp";
2250 reg-names = "l2sram", "l1pram", "l1dram";
2252 ti,sci-dev-id = <143>;
2253 ti,sci-proc-ids = <0x04 0xff>;
2255 firmware-name = "j7-c66_1-fw";
2260 compatible = "ti,j721e-c71-dsp";
2263 reg-names = "l2sram", "l1dram";
2265 ti,sci-dev-id = <15>;
2266 ti,sci-proc-ids = <0x30 0xff>;
2268 firmware-name = "j7-c71_0-fw";
2273 compatible = "ti,j721e-icssg";
2275 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
2276 #address-cells = <1>;
2277 #size-cells = <1>;
2284 reg-names = "dram0", "dram1",
2289 compatible = "ti,pruss-cfg", "syscon";
2291 #address-cells = <1>;
2292 #size-cells = <1>;
2296 #address-cells = <1>;
2297 #size-cells = <0>;
2299 icssg0_coreclk_mux: coreclk-mux@3c {
2301 #clock-cells = <0>;
2304 assigned-clocks = <&icssg0_coreclk_mux>;
2305 assigned-clock-parents = <&k3_clks 119 1>;
2308 icssg0_iepclk_mux: iepclk-mux@30 {
2310 #clock-cells = <0>;
2313 assigned-clocks = <&icssg0_iepclk_mux>;
2314 assigned-clock-parents = <&icssg0_coreclk_mux>;
2319 icssg0_mii_rt: mii-rt@32000 {
2320 compatible = "ti,pruss-mii", "syscon";
2324 icssg0_mii_g_rt: mii-g-rt@33000 {
2325 compatible = "ti,pruss-mii-g", "syscon";
2329 icssg0_intc: interrupt-controller@20000 {
2330 compatible = "ti,icssg-intc";
2332 interrupt-controller;
2333 #interrupt-cells = <3>;
2342 interrupt-names = "host_intr0", "host_intr1",
2349 compatible = "ti,j721e-pru";
2353 reg-names = "iram", "control", "debug";
2354 firmware-name = "j7-pru0_0-fw";
2358 compatible = "ti,j721e-rtu";
2362 reg-names = "iram", "control", "debug";
2363 firmware-name = "j7-rtu0_0-fw";
2367 compatible = "ti,j721e-tx-pru";
2371 reg-names = "iram", "control", "debug";
2372 firmware-name = "j7-txpru0_0-fw";
2376 compatible = "ti,j721e-pru";
2380 reg-names = "iram", "control", "debug";
2381 firmware-name = "j7-pru0_1-fw";
2385 compatible = "ti,j721e-rtu";
2389 reg-names = "iram", "control", "debug";
2390 firmware-name = "j7-rtu0_1-fw";
2394 compatible = "ti,j721e-tx-pru";
2398 reg-names = "iram", "control", "debug";
2399 firmware-name = "j7-txpru0_1-fw";
2406 clock-names = "fck";
2407 #address-cells = <1>;
2408 #size-cells = <0>;
2415 compatible = "ti,j721e-icssg";
2417 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
2418 #address-cells = <1>;
2419 #size-cells = <1>;
2426 reg-names = "dram0", "dram1",
2431 compatible = "ti,pruss-cfg", "syscon";
2433 #address-cells = <1>;
2434 #size-cells = <1>;
2438 #address-cells = <1>;
2439 #size-cells = <0>;
2441 icssg1_coreclk_mux: coreclk-mux@3c {
2443 #clock-cells = <0>;
2446 assigned-clocks = <&icssg1_coreclk_mux>;
2447 assigned-clock-parents = <&k3_clks 120 4>;
2450 icssg1_iepclk_mux: iepclk-mux@30 {
2452 #clock-cells = <0>;
2455 assigned-clocks = <&icssg1_iepclk_mux>;
2456 assigned-clock-parents = <&icssg1_coreclk_mux>;
2461 icssg1_mii_rt: mii-rt@32000 {
2462 compatible = "ti,pruss-mii", "syscon";
2466 icssg1_mii_g_rt: mii-g-rt@33000 {
2467 compatible = "ti,pruss-mii-g", "syscon";
2471 icssg1_intc: interrupt-controller@20000 {
2472 compatible = "ti,icssg-intc";
2474 interrupt-controller;
2475 #interrupt-cells = <3>;
2484 interrupt-names = "host_intr0", "host_intr1",
2491 compatible = "ti,j721e-pru";
2495 reg-names = "iram", "control", "debug";
2496 firmware-name = "j7-pru1_0-fw";
2500 compatible = "ti,j721e-rtu";
2504 reg-names = "iram", "control", "debug";
2505 firmware-name = "j7-rtu1_0-fw";
2509 compatible = "ti,j721e-tx-pru";
2513 reg-names = "iram", "control", "debug";
2514 firmware-name = "j7-txpru1_0-fw";
2518 compatible = "ti,j721e-pru";
2522 reg-names = "iram", "control", "debug";
2523 firmware-name = "j7-pru1_1-fw";
2527 compatible = "ti,j721e-rtu";
2531 reg-names = "iram", "control", "debug";
2532 firmware-name = "j7-rtu1_1-fw";
2536 compatible = "ti,j721e-tx-pru";
2540 reg-names = "iram", "control", "debug";
2541 firmware-name = "j7-txpru1_1-fw";
2548 clock-names = "fck";
2549 #address-cells = <1>;
2550 #size-cells = <0>;
2560 reg-names = "m_can", "message_ram";
2561 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2563 clock-names = "hclk", "cclk";
2566 interrupt-names = "int0", "int1";
2567 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2575 reg-names = "m_can", "message_ram";
2576 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2578 clock-names = "hclk", "cclk";
2581 interrupt-names = "int0", "int1";
2582 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2590 reg-names = "m_can", "message_ram";
2591 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2593 clock-names = "hclk", "cclk";
2596 interrupt-names = "int0", "int1";
2597 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2605 reg-names = "m_can", "message_ram";
2606 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2608 clock-names = "hclk", "cclk";
2611 interrupt-names = "int0", "int1";
2612 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2620 reg-names = "m_can", "message_ram";
2621 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2623 clock-names = "hclk", "cclk";
2626 interrupt-names = "int0", "int1";
2627 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2635 reg-names = "m_can", "message_ram";
2636 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2638 clock-names = "hclk", "cclk";
2641 interrupt-names = "int0", "int1";
2642 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2650 reg-names = "m_can", "message_ram";
2651 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2653 clock-names = "hclk", "cclk";
2656 interrupt-names = "int0", "int1";
2657 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2665 reg-names = "m_can", "message_ram";
2666 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2668 clock-names = "hclk", "cclk";
2671 interrupt-names = "int0", "int1";
2672 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2680 reg-names = "m_can", "message_ram";
2681 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2683 clock-names = "hclk", "cclk";
2686 interrupt-names = "int0", "int1";
2687 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2695 reg-names = "m_can", "message_ram";
2696 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2698 clock-names = "hclk", "cclk";
2701 interrupt-names = "int0", "int1";
2702 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2710 reg-names = "m_can", "message_ram";
2711 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2713 clock-names = "hclk", "cclk";
2716 interrupt-names = "int0", "int1";
2717 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2725 reg-names = "m_can", "message_ram";
2726 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2728 clock-names = "hclk", "cclk";
2731 interrupt-names = "int0", "int1";
2732 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2740 reg-names = "m_can", "message_ram";
2741 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2743 clock-names = "hclk", "cclk";
2746 interrupt-names = "int0", "int1";
2747 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2755 reg-names = "m_can", "message_ram";
2756 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2758 clock-names = "hclk", "cclk";
2761 interrupt-names = "int0", "int1";
2762 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2767 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2770 #address-cells = <1>;
2771 #size-cells = <0>;
2772 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
2778 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2781 #address-cells = <1>;
2782 #size-cells = <0>;
2783 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
2789 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2792 #address-cells = <1>;
2793 #size-cells = <0>;
2794 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
2800 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2803 #address-cells = <1>;
2804 #size-cells = <0>;
2805 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
2811 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2814 #address-cells = <1>;
2815 #size-cells = <0>;
2816 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
2822 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2825 #address-cells = <1>;
2826 #size-cells = <0>;
2827 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
2833 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2836 #address-cells = <1>;
2837 #size-cells = <0>;
2838 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
2844 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2847 #address-cells = <1>;
2848 #size-cells = <0>;
2849 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
2855 compatible = "ti,j721e-esm";
2857 bootph-pre-ram;
2858 ti,esm-pins = <344>, <345>;