Lines Matching +full:auxclk +full:- +full:fs +full:- +full:ratio
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e-som-p0.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
14 #include <dt-bindings/phy/phy-cadence.h>
17 compatible = "ti,j721e-evm", "ti,j721e";
33 stdout-path = "serial2:115200n8";
36 gpio_keys: gpio-keys {
37 compatible = "gpio-keys";
39 pinctrl-names = "default";
40 pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;
42 sw10: switch-10 {
48 sw11: switch-11 {
55 evm_12v0: fixedregulator-evm12v0 {
57 compatible = "regulator-fixed";
58 regulator-name = "evm_12v0";
59 regulator-min-microvolt = <12000000>;
60 regulator-max-microvolt = <12000000>;
61 regulator-always-on;
62 regulator-boot-on;
65 vsys_3v3: fixedregulator-vsys3v3 {
67 compatible = "regulator-fixed";
68 regulator-name = "vsys_3v3";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 vin-supply = <&evm_12v0>;
72 regulator-always-on;
73 regulator-boot-on;
76 vsys_5v0: fixedregulator-vsys5v0 {
78 compatible = "regulator-fixed";
79 regulator-name = "vsys_5v0";
80 regulator-min-microvolt = <5000000>;
81 regulator-max-microvolt = <5000000>;
82 vin-supply = <&evm_12v0>;
83 regulator-always-on;
84 regulator-boot-on;
87 vdd_mmc1: fixedregulator-sd {
88 compatible = "regulator-fixed";
89 regulator-name = "vdd_mmc1";
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
92 regulator-boot-on;
93 enable-active-high;
94 vin-supply = <&vsys_3v3>;
98 vdd_sd_dv_alt: gpio-regulator-TLV71033 {
99 compatible = "regulator-gpio";
100 pinctrl-names = "default";
101 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
102 regulator-name = "tlv71033";
103 regulator-min-microvolt = <1800000>;
104 regulator-max-microvolt = <3300000>;
105 regulator-boot-on;
106 vin-supply = <&vsys_5v0>;
112 sound0: sound-0 {
113 compatible = "ti,j721e-cpb-audio";
114 model = "j721e-cpb";
116 ti,cpb-mcasp = <&mcasp10>;
117 ti,cpb-codec = <&pcm3168a_1>;
123 clock-names = "cpb-mcasp-auxclk",
124 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
125 "cpb-codec-scki",
126 "cpb-codec-scki-48000", "cpb-codec-scki-44100";
129 transceiver1: can-phy0 {
131 #phy-cells = <0>;
132 max-bitrate = <5000000>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
135 standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
136 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
139 transceiver2: can-phy1 {
141 #phy-cells = <0>;
142 max-bitrate = <5000000>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
145 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
148 transceiver3: can-phy2 {
150 #phy-cells = <0>;
151 max-bitrate = <5000000>;
152 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
153 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
156 transceiver4: can-phy3 {
158 #phy-cells = <0>;
159 max-bitrate = <5000000>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&main_mcan2_gpio_pins_default>;
162 standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
165 dp_pwr_3v3: regulator-dp-pwr {
166 compatible = "regulator-fixed";
167 regulator-name = "dp-pwr";
168 regulator-min-microvolt = <3300000>;
169 regulator-max-microvolt = <3300000>;
170 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
171 enable-active-high;
175 compatible = "dp-connector";
177 type = "full-size";
178 dp-pwr-supply = <&dp_pwr_3v3>;
182 remote-endpoint = <&dp0_out>;
189 main_uart0_pins_default: main-uart0-default-pins {
190 pinctrl-single,pins = <
196 bootph-all;
199 main_uart1_pins_default: main-uart1-default-pins {
200 pinctrl-single,pins = <
206 main_uart2_pins_default: main-uart2-default-pins {
207 pinctrl-single,pins = <
213 main_uart4_pins_default: main-uart4-default-pins {
214 pinctrl-single,pins = <
220 sw10_button_pins_default: sw10-button-default-pins {
221 pinctrl-single,pins = <
226 main_mmc1_pins_default: main-mmc1-default-pins {
227 pinctrl-single,pins = <
238 bootph-all;
241 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
242 pinctrl-single,pins = <
247 main_usbss0_pins_default: main-usbss0-default-pins {
248 pinctrl-single,pins = <
252 bootph-all;
255 main_usbss1_pins_default: main-usbss1-default-pins {
256 pinctrl-single,pins = <
261 dp0_pins_default: dp0-default-pins {
262 pinctrl-single,pins = <
267 main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins {
268 pinctrl-single,pins = <
273 main_i2c0_pins_default: main-i2c0-default-pins {
274 pinctrl-single,pins = <
280 main_i2c1_pins_default: main-i2c1-default-pins {
281 pinctrl-single,pins = <
287 main_i2c3_pins_default: main-i2c3-default-pins {
288 pinctrl-single,pins = <
294 main_i2c6_pins_default: main-i2c6-default-pins {
295 pinctrl-single,pins = <
301 mcasp10_pins_default: mcasp10-default-pins {
302 pinctrl-single,pins = <
315 audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins {
316 pinctrl-single,pins = <
321 main_mcan0_pins_default: main-mcan0-default-pins {
322 pinctrl-single,pins = <
328 main_mcan2_pins_default: main-mcan2-default-pins {
329 pinctrl-single,pins = <
335 main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins {
336 pinctrl-single,pins = <
343 wkup_uart0_pins_default: wkup-uart0-default-pins {
344 pinctrl-single,pins = <
348 bootph-all;
351 mcu_uart0_pins_default: mcu-uart0-default-pins {
352 pinctrl-single,pins = <
358 bootph-all;
361 sw11_button_pins_default: sw11-button-default-pins {
362 pinctrl-single,pins = <
367 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
368 pinctrl-single,pins = <
378 bootph-all;
381 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
382 pinctrl-single,pins = <
398 mcu_mdio_pins_default: mcu-mdio1-default-pins {
399 pinctrl-single,pins = <
405 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
406 pinctrl-single,pins = <
412 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
413 pinctrl-single,pins = <
419 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
420 pinctrl-single,pins = <
426 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
427 pinctrl-single,pins = <
432 wkup_gpio_pins_default: wkup-gpio-default-pins {
433 pinctrl-single,pins = <
442 pinctrl-names = "default";
443 pinctrl-0 = <&wkup_uart0_pins_default>;
444 bootph-all;
449 pinctrl-names = "default";
450 pinctrl-0 = <&mcu_uart0_pins_default>;
451 bootph-all;
456 pinctrl-names = "default";
457 pinctrl-0 = <&main_uart0_pins_default>;
459 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
460 bootph-all;
465 pinctrl-names = "default";
466 pinctrl-0 = <&main_uart1_pins_default>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&main_uart2_pins_default>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&main_uart4_pins_default>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&wkup_gpio_pins_default>;
498 non-removable;
499 bootph-all;
500 ti,driver-strength-ohm = <50>;
501 disable-wp;
507 vmmc-supply = <&vdd_mmc1>;
508 vqmmc-supply = <&vdd_sd_dv_alt>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&main_mmc1_pins_default>;
511 bootph-all;
512 ti,driver-strength-ohm = <50>;
513 disable-wp;
517 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
518 bootph-all;
522 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
528 bootph-all;
532 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
533 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
539 cdns,num-lanes = <2>;
540 #phy-cells = <0>;
541 cdns,phy-type = <PHY_TYPE_USB3>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&main_usbss0_pins_default>;
549 bootph-all;
550 ti,vbus-divider;
555 maximum-speed = "super-speed";
557 phy-names = "cdns3,usb3-phy";
558 bootph-all;
562 pinctrl-names = "default";
563 pinctrl-0 = <&main_usbss1_pins_default>;
564 ti,usb2-only;
569 maximum-speed = "high-speed";
573 pinctrl-names = "default";
574 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
577 compatible = "jedec,spi-nor";
579 spi-tx-bus-width = <1>;
580 spi-rx-bus-width = <4>;
581 spi-max-frequency = <40000000>;
582 cdns,tshsl-ns = <60>;
583 cdns,tsd2d-ns = <60>;
584 cdns,tchsh-ns = <60>;
585 cdns,tslch-ns = <60>;
586 cdns,read-delay = <2>;
589 compatible = "fixed-partitions";
590 #address-cells = <1>;
591 #size-cells = <1>;
604 label = "qspi.u-boot";
631 bootph-all;
640 ti,adc-channels = <0 1 2 3 4 5 6 7>;
647 ti,adc-channels = <0 1 2 3 4 5 6 7>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&main_i2c0_pins_default>;
655 clock-frequency = <400000>;
660 gpio-controller;
661 #gpio-cells = <2>;
667 gpio-controller;
668 #gpio-cells = <2>;
670 p09-hog {
671 /* P11 - MCASP/TRACE_MUX_S0 */
672 gpio-hog;
674 output-low;
675 line-name = "MCASP/TRACE_MUX_S0";
678 p10-hog {
679 /* P12 - MCASP/TRACE_MUX_S1 */
680 gpio-hog;
682 output-high;
683 line-name = "MCASP/TRACE_MUX_S1";
690 pinctrl-names = "default";
691 pinctrl-0 = <&main_i2c1_pins_default>;
692 clock-frequency = <400000>;
697 gpio-controller;
698 #gpio-cells = <2>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&main_i2c1_exp4_pins_default>;
701 interrupt-parent = <&main_gpio1>;
703 interrupt-controller;
704 #interrupt-cells = <2>;
710 pinctrl-names = "default";
711 pinctrl-0 = <&audi_ext_refclk2_pins_default>;
716 pinctrl-names = "default";
717 pinctrl-0 = <&main_i2c3_pins_default>;
718 clock-frequency = <400000>;
723 gpio-controller;
724 #gpio-cells = <2>;
727 pcm3168a_1: audio-codec@44 {
731 #sound-dai-cells = <1>;
733 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
735 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
737 clock-names = "scki";
739 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
740 assigned-clocks = <&k3_clks 157 371>;
741 assigned-clock-parents = <&k3_clks 157 400>;
742 assigned-clock-rates = <24576000>; /* for 48KHz */
744 VDD1-supply = <&vsys_3v3>;
745 VDD2-supply = <&vsys_3v3>;
746 VCCAD1-supply = <&vsys_5v0>;
747 VCCAD2-supply = <&vsys_5v0>;
748 VCCDA1-supply = <&vsys_5v0>;
749 VCCDA2-supply = <&vsys_5v0>;
755 pinctrl-names = "default";
756 pinctrl-0 = <&main_i2c6_pins_default>;
757 clock-frequency = <400000>;
762 gpio-controller;
763 #gpio-cells = <2>;
768 pinctrl-names = "default";
769 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
773 phy0: ethernet-phy@0 {
775 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
776 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
781 phy-mode = "rgmii-rxid";
782 phy-handle = <&phy0>;
789 * VP0 - DisplayPort SST
790 * VP1 - DPI0
791 * VP2 - DSI
792 * VP3 - DPI1
795 assigned-clocks = <&k3_clks 152 1>,
799 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
808 remote-endpoint = <&dp0_in>;
814 #address-cells = <1>;
815 #size-cells = <0>;
820 remote-endpoint = <&dpi0_out>;
827 remote-endpoint = <&dp_connector_in>;
834 #sound-dai-cells = <0>;
836 pinctrl-names = "default";
837 pinctrl-0 = <&mcasp10_pins_default>;
839 op-mode = <0>; /* MCASP_IIS_MODE */
840 tdm-slots = <2>;
841 auxclk-fs-ratio = <256>;
843 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
847 tx-num-evt = <0>;
848 rx-num-evt = <0>;
852 clock-frequency = <100000000>;
856 assigned-clocks = <&wiz0_pll1_refclk>;
857 assigned-clock-parents = <&cmn_refclk1>;
861 assigned-clocks = <&wiz0_refclk_dig>;
862 assigned-clock-parents = <&cmn_refclk1>;
866 assigned-clocks = <&wiz1_pll1_refclk>;
867 assigned-clock-parents = <&cmn_refclk1>;
871 assigned-clocks = <&wiz1_refclk_dig>;
872 assigned-clock-parents = <&cmn_refclk1>;
876 assigned-clocks = <&wiz2_pll1_refclk>;
877 assigned-clock-parents = <&cmn_refclk1>;
881 assigned-clocks = <&wiz2_refclk_dig>;
882 assigned-clock-parents = <&cmn_refclk1>;
886 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
887 assigned-clock-parents = <&wiz0_pll1_refclk>;
891 cdns,num-lanes = <1>;
892 #phy-cells = <0>;
893 cdns,phy-type = <PHY_TYPE_PCIE>;
899 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
900 assigned-clock-parents = <&wiz1_pll1_refclk>;
904 cdns,num-lanes = <2>;
905 #phy-cells = <0>;
906 cdns,phy-type = <PHY_TYPE_PCIE>;
912 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
913 assigned-clock-parents = <&wiz2_pll1_refclk>;
917 cdns,num-lanes = <2>;
918 #phy-cells = <0>;
919 cdns,phy-type = <PHY_TYPE_PCIE>;
928 cdns,phy-type = <PHY_TYPE_DP>;
929 cdns,num-lanes = <4>;
930 cdns,max-bit-rate = <5400>;
931 #phy-cells = <0>;
937 phy-names = "dpphy";
938 pinctrl-names = "default";
939 pinctrl-0 = <&dp0_pins_default>;
944 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
946 phy-names = "pcie-phy";
947 num-lanes = <1>;
952 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
954 phy-names = "pcie-phy";
955 num-lanes = <2>;
960 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
962 phy-names = "pcie-phy";
963 num-lanes = <2>;
968 pinctrl-names = "default";
969 pinctrl-0 = <&mcu_mcan0_pins_default>;
975 pinctrl-names = "default";
976 pinctrl-0 = <&mcu_mcan1_pins_default>;
982 pinctrl-names = "default";
983 pinctrl-0 = <&main_mcan0_pins_default>;
989 pinctrl-names = "default";
990 pinctrl-0 = <&main_mcan2_pins_default>;