Lines Matching +full:sci +full:- +full:pm +full:- +full:domain
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
24 bootph-all;
27 k3_clks: clock-controller {
28 compatible = "ti,k2g-sci-clk";
29 #clock-cells = <2>;
30 bootph-all;
33 k3_reset: reset-controller {
34 compatible = "ti,sci-reset";
35 #reset-cells = <2>;
36 bootph-all;
42 compatible = "ti,am654-timer";
46 clock-names = "fck";
47 assigned-clocks = <&k3_clks 35 1>;
48 assigned-clock-parents = <&k3_clks 35 2>;
49 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
50 bootph-pre-ram;
51 ti,timer-pwm;
56 compatible = "ti,am654-timer";
60 clock-names = "fck";
61 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
62 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
63 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
64 ti,timer-pwm;
69 compatible = "ti,am654-timer";
73 clock-names = "fck";
74 assigned-clocks = <&k3_clks 72 1>;
75 assigned-clock-parents = <&k3_clks 72 2>;
76 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
77 ti,timer-pwm;
82 compatible = "ti,am654-timer";
86 clock-names = "fck";
87 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
88 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
89 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
90 ti,timer-pwm;
95 compatible = "ti,am654-timer";
99 clock-names = "fck";
100 assigned-clocks = <&k3_clks 74 1>;
101 assigned-clock-parents = <&k3_clks 74 2>;
102 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
103 ti,timer-pwm;
108 compatible = "ti,am654-timer";
112 clock-names = "fck";
113 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
114 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>;
115 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
116 ti,timer-pwm;
121 compatible = "ti,am654-timer";
125 clock-names = "fck";
126 assigned-clocks = <&k3_clks 76 1>;
127 assigned-clock-parents = <&k3_clks 76 2>;
128 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
129 ti,timer-pwm;
134 compatible = "ti,am654-timer";
138 clock-names = "fck";
139 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
140 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>;
141 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
142 ti,timer-pwm;
147 compatible = "ti,am654-timer";
151 clock-names = "fck";
152 assigned-clocks = <&k3_clks 78 1>;
153 assigned-clock-parents = <&k3_clks 78 2>;
154 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
155 ti,timer-pwm;
160 compatible = "ti,am654-timer";
164 clock-names = "fck";
165 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
166 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>;
167 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
168 ti,timer-pwm;
172 compatible = "simple-bus";
173 #address-cells = <1>;
174 #size-cells = <1>;
177 cpsw_mac_syscon: ethernet-mac-syscon@200 {
178 compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
183 compatible = "ti,am654-phy-gmii-sel";
185 #phy-cells = <1>;
188 spi1_linkdis: mux-controller@4060 {
189 compatible = "reg-mux";
191 #mux-control-cells = <1>;
192 mux-reg-masks = <0x0 0x1>;
197 compatible = "simple-bus";
198 #address-cells = <1>;
199 #size-cells = <1>;
203 compatible = "ti,am654-chipid";
205 bootph-all;
211 compatible = "ti,j7200-padconf", "pinctrl-single";
213 #pinctrl-cells = <1>;
214 pinctrl-single,register-width = <32>;
215 pinctrl-single,function-mask = <0x0000000F>;
221 compatible = "ti,j7200-padconf", "pinctrl-single";
223 #pinctrl-cells = <1>;
224 pinctrl-single,register-width = <32>;
225 pinctrl-single,function-mask = <0x0000000F>;
230 compatible = "ti,j7200-padconf", "pinctrl-single";
233 #pinctrl-cells = <1>;
234 pinctrl-single,register-width = <32>;
235 pinctrl-single,function-mask = <0xffffffff>;
239 compatible = "ti,j7200-padconf", "pinctrl-single";
242 #pinctrl-cells = <1>;
243 pinctrl-single,register-width = <32>;
244 pinctrl-single,function-mask = <0xffffffff>;
248 compatible = "ti,j7200-padconf", "pinctrl-single";
251 #pinctrl-cells = <1>;
252 pinctrl-single,register-width = <32>;
253 pinctrl-single,function-mask = <0xffffffff>;
257 compatible = "ti,j7200-padconf", "pinctrl-single";
260 #pinctrl-cells = <1>;
261 pinctrl-single,register-width = <32>;
262 pinctrl-single,function-mask = <0xffffffff>;
266 compatible = "mmio-sram";
269 #address-cells = <1>;
270 #size-cells = <1>;
274 compatible = "ti,j721e-uart", "ti,am654-uart";
277 clock-frequency = <48000000>;
278 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
280 clock-names = "fclk";
285 compatible = "ti,j721e-uart", "ti,am654-uart";
288 clock-frequency = <96000000>;
289 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
291 clock-names = "fclk";
295 wkup_gpio_intr: interrupt-controller@42200000 {
296 compatible = "ti,sci-intr";
298 ti,intr-trigger-type = <1>;
299 interrupt-controller;
300 interrupt-parent = <&gic500>;
301 #interrupt-cells = <1>;
302 ti,sci = <&dmsc>;
303 ti,sci-dev-id = <137>;
304 ti,interrupt-ranges = <16 960 16>;
308 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-parent = <&wkup_gpio_intr>;
314 interrupt-controller;
315 #interrupt-cells = <2>;
317 ti,davinci-gpio-unbanked = <0>;
318 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
320 clock-names = "gpio";
325 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
327 gpio-controller;
328 #gpio-cells = <2>;
329 interrupt-parent = <&wkup_gpio_intr>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
334 ti,davinci-gpio-unbanked = <0>;
335 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
337 clock-names = "gpio";
342 compatible = "simple-bus";
343 #address-cells = <2>;
344 #size-cells = <2>;
346 dma-coherent;
347 dma-ranges;
348 ti,sci-dev-id = <232>;
351 compatible = "ti,am654-navss-ringacc";
357 reg-names = "rt", "fifos", "proxy_gcfg",
359 bootph-all;
360 ti,num-rings = <286>;
361 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
362 ti,sci = <&dmsc>;
363 ti,sci-dev-id = <235>;
364 msi-parent = <&main_udmass_inta>;
367 mcu_udmap: dma-controller@285c0000 {
368 compatible = "ti,j721e-navss-mcu-udmap";
375 reg-names = "gcfg", "rchanrt", "tchanrt",
377 msi-parent = <&main_udmass_inta>;
378 #dma-cells = <1>;
379 bootph-all;
381 ti,sci = <&dmsc>;
382 ti,sci-dev-id = <236>;
385 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
387 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
389 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
394 compatible = "ti,am654-secure-proxy";
395 #mbox-cells = <1>;
396 reg-names = "target_data", "rt", "scfg";
400 bootph-pre-ram;
405 * firmware on non-MPU processors
411 compatible = "ti,j721e-cpsw-nuss";
412 #address-cells = <2>;
413 #size-cells = <2>;
415 reg-names = "cpsw_nuss";
417 dma-coherent;
419 clock-names = "fck";
420 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
431 dma-names = "tx0", "tx1", "tx2", "tx3",
435 ethernet-ports {
436 #address-cells = <1>;
437 #size-cells = <0>;
441 ti,mac-only;
443 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
449 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
451 #address-cells = <1>;
452 #size-cells = <0>;
454 clock-names = "fck";
459 compatible = "ti,am65-cpts";
462 clock-names = "cpts";
463 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
464 interrupt-names = "cpts";
465 ti,cpts-ext-ts-inputs = <4>;
466 ti,cpts-periodic-outputs = <2>;
471 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
474 #address-cells = <1>;
475 #size-cells = <0>;
476 clock-names = "fck";
478 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
483 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
486 #address-cells = <1>;
487 #size-cells = <0>;
488 clock-names = "fck";
490 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
495 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
498 #address-cells = <1>;
499 #size-cells = <0>;
500 clock-names = "fck";
502 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
507 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
510 #address-cells = <1>;
511 #size-cells = <0>;
512 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
518 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
521 #address-cells = <1>;
522 #size-cells = <0>;
523 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
529 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
532 #address-cells = <1>;
533 #size-cells = <0>;
534 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
540 compatible = "simple-bus";
541 #address-cells = <2>;
542 #size-cells = <2>;
548 hbmc_mux: mux-controller@47000004 {
549 compatible = "reg-mux";
551 #mux-control-cells = <1>;
552 mux-reg-masks = <0x0 0x2>; /* HBMC select */
553 bootph-all;
557 compatible = "ti,am654-hbmc";
560 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
562 assigned-clocks = <&k3_clks 102 5>;
563 assigned-clock-rates = <333333333>;
564 #address-cells = <2>;
565 #size-cells = <1>;
566 mux-controls = <&hbmc_mux 0>;
570 compatible = "ti,am654-ospi", "cdns,qspi-nor";
574 cdns,fifo-depth = <256>;
575 cdns,fifo-width = <4>;
576 cdns,trigger-address = <0x0>;
578 assigned-clocks = <&k3_clks 103 0>;
579 assigned-clock-parents = <&k3_clks 103 2>;
580 assigned-clock-rates = <166666666>;
581 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
582 #address-cells = <1>;
583 #size-cells = <0>;
589 compatible = "ti,am3359-tscadc";
592 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
594 assigned-clocks = <&k3_clks 0 3>;
595 assigned-clock-rates = <60000000>;
596 clock-names = "fck";
599 dma-names = "fifo0", "fifo1";
602 #io-channel-cells = <1>;
603 compatible = "ti,am3359-adc";
608 compatible = "ti,j7200-r5fss";
609 ti,cluster-mode = <1>;
610 #address-cells = <1>;
611 #size-cells = <1>;
614 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
617 compatible = "ti,j7200-r5f";
620 reg-names = "atcm", "btcm";
621 ti,sci = <&dmsc>;
622 ti,sci-dev-id = <250>;
623 ti,sci-proc-ids = <0x01 0xff>;
625 firmware-name = "j7200-mcu-r5f0_0-fw";
626 ti,atcm-enable = <1>;
627 ti,btcm-enable = <1>;
632 compatible = "ti,j7200-r5f";
635 reg-names = "atcm", "btcm";
636 ti,sci = <&dmsc>;
637 ti,sci-dev-id = <251>;
638 ti,sci-proc-ids = <0x02 0xff>;
640 firmware-name = "j7200-mcu-r5f0_1-fw";
641 ti,atcm-enable = <1>;
642 ti,btcm-enable = <1>;
648 compatible = "ti,j721e-sa2ul";
650 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
651 #address-cells = <2>;
652 #size-cells = <2>;
656 dma-names = "tx", "rx1", "rx2";
659 compatible = "inside-secure,safexcel-eip76";
662 status = "disabled"; /* Used by OP-TEE */
666 wkup_vtm0: temperature-sensor@42040000 {
667 compatible = "ti,j7200-vtm";
670 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
671 #thermal-sensor-cells = <1>;
672 bootph-pre-ram;
676 compatible = "ti,j721e-esm";
678 ti,esm-pins = <95>;
679 bootph-pre-ram;
686 reg-names = "m_can", "message_ram";
687 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
689 clock-names = "hclk", "cclk";
692 interrupt-names = "int0", "int1";
693 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
701 reg-names = "m_can", "message_ram";
702 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
704 clock-names = "hclk", "cclk";
707 interrupt-names = "int0", "int1";
708 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;