Lines Matching +full:assigned +full:- +full:clocks
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 serdes_ln_ctrl: mux-controller@4080 {
36 compatible = "reg-mux";
38 #mux-control-cells = <1>;
39 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
44 compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
45 ti,qsgmii-main-ports = <1>;
47 #phy-cells = <1>;
50 usb_serdes_mux: mux-controller@4000 {
51 compatible = "reg-mux";
53 #mux-control-cells = <1>;
54 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
58 gic500: interrupt-controller@1800000 {
59 compatible = "arm,gic-v3";
60 #address-cells = <2>;
61 #size-cells = <2>;
63 #interrupt-cells = <3>;
64 interrupt-controller;
74 gic_its: msi-controller@1820000 {
75 compatible = "arm,gic-v3-its";
77 socionext,synquacer-pre-its = <0x1000000 0x400000>;
78 msi-controller;
79 #msi-cells = <1>;
83 main_gpio_intr: interrupt-controller@a00000 {
84 compatible = "ti,sci-intr";
86 ti,intr-trigger-type = <1>;
87 interrupt-controller;
88 interrupt-parent = <&gic500>;
89 #interrupt-cells = <1>;
91 ti,sci-dev-id = <131>;
92 ti,interrupt-ranges = <8 392 56>;
96 compatible = "simple-bus";
97 #address-cells = <2>;
98 #size-cells = <2>;
100 ti,sci-dev-id = <199>;
101 dma-coherent;
102 dma-ranges;
104 main_navss_intr: interrupt-controller@310e0000 {
105 compatible = "ti,sci-intr";
107 ti,intr-trigger-type = <4>;
108 interrupt-controller;
109 interrupt-parent = <&gic500>;
110 #interrupt-cells = <1>;
112 ti,sci-dev-id = <213>;
113 ti,interrupt-ranges = <0 64 64>,
118 main_udmass_inta: msi-controller@33d00000 {
119 compatible = "ti,sci-inta";
121 interrupt-controller;
122 #interrupt-cells = <0>;
123 interrupt-parent = <&main_navss_intr>;
124 msi-controller;
126 ti,sci-dev-id = <209>;
127 ti,interrupt-ranges = <0 0 256>;
131 compatible = "ti,am654-secure-proxy";
132 #mbox-cells = <1>;
133 reg-names = "target_data", "rt", "scfg";
137 interrupt-names = "rx_011";
139 bootph-all;
143 compatible = "ti,am654-hwspinlock";
145 #hwlock-cells = <1>;
149 compatible = "ti,am654-mailbox";
151 #mbox-cells = <1>;
152 ti,mbox-num-users = <4>;
153 ti,mbox-num-fifos = <16>;
154 interrupt-parent = <&main_navss_intr>;
159 compatible = "ti,am654-mailbox";
161 #mbox-cells = <1>;
162 ti,mbox-num-users = <4>;
163 ti,mbox-num-fifos = <16>;
164 interrupt-parent = <&main_navss_intr>;
169 compatible = "ti,am654-mailbox";
171 #mbox-cells = <1>;
172 ti,mbox-num-users = <4>;
173 ti,mbox-num-fifos = <16>;
174 interrupt-parent = <&main_navss_intr>;
179 compatible = "ti,am654-mailbox";
181 #mbox-cells = <1>;
182 ti,mbox-num-users = <4>;
183 ti,mbox-num-fifos = <16>;
184 interrupt-parent = <&main_navss_intr>;
189 compatible = "ti,am654-mailbox";
191 #mbox-cells = <1>;
192 ti,mbox-num-users = <4>;
193 ti,mbox-num-fifos = <16>;
194 interrupt-parent = <&main_navss_intr>;
199 compatible = "ti,am654-mailbox";
201 #mbox-cells = <1>;
202 ti,mbox-num-users = <4>;
203 ti,mbox-num-fifos = <16>;
204 interrupt-parent = <&main_navss_intr>;
209 compatible = "ti,am654-mailbox";
211 #mbox-cells = <1>;
212 ti,mbox-num-users = <4>;
213 ti,mbox-num-fifos = <16>;
214 interrupt-parent = <&main_navss_intr>;
219 compatible = "ti,am654-mailbox";
221 #mbox-cells = <1>;
222 ti,mbox-num-users = <4>;
223 ti,mbox-num-fifos = <16>;
224 interrupt-parent = <&main_navss_intr>;
229 compatible = "ti,am654-mailbox";
231 #mbox-cells = <1>;
232 ti,mbox-num-users = <4>;
233 ti,mbox-num-fifos = <16>;
234 interrupt-parent = <&main_navss_intr>;
239 compatible = "ti,am654-mailbox";
241 #mbox-cells = <1>;
242 ti,mbox-num-users = <4>;
243 ti,mbox-num-fifos = <16>;
244 interrupt-parent = <&main_navss_intr>;
249 compatible = "ti,am654-mailbox";
251 #mbox-cells = <1>;
252 ti,mbox-num-users = <4>;
253 ti,mbox-num-fifos = <16>;
254 interrupt-parent = <&main_navss_intr>;
259 compatible = "ti,am654-mailbox";
261 #mbox-cells = <1>;
262 ti,mbox-num-users = <4>;
263 ti,mbox-num-fifos = <16>;
264 interrupt-parent = <&main_navss_intr>;
269 compatible = "ti,am654-navss-ringacc";
275 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
276 ti,num-rings = <1024>;
277 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
279 ti,sci-dev-id = <211>;
280 msi-parent = <&main_udmass_inta>;
283 main_udmap: dma-controller@31150000 {
284 compatible = "ti,j721e-navss-main-udmap";
291 reg-names = "gcfg", "rchanrt", "tchanrt",
293 msi-parent = <&main_udmass_inta>;
294 #dma-cells = <1>;
297 ti,sci-dev-id = <212>;
300 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
303 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
306 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
310 compatible = "ti,j721e-cpts";
312 reg-names = "cpts";
313 clocks = <&k3_clks 201 1>;
314 clock-names = "cpts";
315 interrupts-extended = <&main_navss_intr 391>;
316 interrupt-names = "cpts";
317 ti,cpts-periodic-outputs = <6>;
318 ti,cpts-ext-ts-inputs = <8>;
323 compatible = "ti,j7200-cpswxg-nuss";
324 #address-cells = <2>;
325 #size-cells = <2>;
327 reg-names = "cpsw_nuss";
329 clocks = <&k3_clks 19 33>;
330 clock-names = "fck";
331 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
342 dma-names = "tx0", "tx1", "tx2", "tx3",
348 ethernet-ports {
349 #address-cells = <1>;
350 #size-cells = <0>;
353 ti,mac-only;
360 ti,mac-only;
367 ti,mac-only;
374 ti,mac-only;
381 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
383 #address-cells = <1>;
384 #size-cells = <0>;
385 clocks = <&k3_clks 19 33>;
386 clock-names = "fck";
392 compatible = "ti,j721e-cpts";
394 clocks = <&k3_clks 19 16>;
395 clock-names = "cpts";
396 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-names = "cpts";
398 ti,cpts-ext-ts-inputs = <4>;
399 ti,cpts-periodic-outputs = <2>;
405 compatible = "ti,j7200-padconf", "pinctrl-single";
407 #pinctrl-cells = <1>;
408 pinctrl-single,register-width = <32>;
409 pinctrl-single,function-mask = <0x000001ff>;
414 compatible = "ti,j7200-padconf", "pinctrl-single";
416 #pinctrl-cells = <1>;
417 pinctrl-single,register-width = <32>;
418 pinctrl-single,function-mask = <0x0000001f>;
422 compatible = "ti,j7200-padconf", "pinctrl-single";
425 #pinctrl-cells = <1>;
426 pinctrl-single,register-width = <32>;
427 pinctrl-single,function-mask = <0xffffffff>;
431 compatible = "ti,j7200-padconf", "pinctrl-single";
434 #pinctrl-cells = <1>;
435 pinctrl-single,register-width = <32>;
436 pinctrl-single,function-mask = <0xffffffff>;
440 compatible = "ti,j7200-padconf", "pinctrl-single";
443 #pinctrl-cells = <1>;
444 pinctrl-single,register-width = <32>;
445 pinctrl-single,function-mask = <0xffffffff>;
449 compatible = "ti,j7200-padconf", "pinctrl-single";
452 #pinctrl-cells = <1>;
453 pinctrl-single,register-width = <32>;
454 pinctrl-single,function-mask = <0xffffffff>;
458 compatible = "ti,j721e-uart", "ti,am654-uart";
461 clock-frequency = <48000000>;
462 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
463 clocks = <&k3_clks 146 2>;
464 clock-names = "fclk";
469 compatible = "ti,j721e-uart", "ti,am654-uart";
472 clock-frequency = <48000000>;
473 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
474 clocks = <&k3_clks 278 2>;
475 clock-names = "fclk";
480 compatible = "ti,j721e-uart", "ti,am654-uart";
483 clock-frequency = <48000000>;
484 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
485 clocks = <&k3_clks 279 2>;
486 clock-names = "fclk";
491 compatible = "ti,j721e-uart", "ti,am654-uart";
494 clock-frequency = <48000000>;
495 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
496 clocks = <&k3_clks 280 2>;
497 clock-names = "fclk";
502 compatible = "ti,j721e-uart", "ti,am654-uart";
505 clock-frequency = <48000000>;
506 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
507 clocks = <&k3_clks 281 2>;
508 clock-names = "fclk";
513 compatible = "ti,j721e-uart", "ti,am654-uart";
516 clock-frequency = <48000000>;
517 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
518 clocks = <&k3_clks 282 2>;
519 clock-names = "fclk";
524 compatible = "ti,j721e-uart", "ti,am654-uart";
527 clock-frequency = <48000000>;
528 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
529 clocks = <&k3_clks 283 2>;
530 clock-names = "fclk";
535 compatible = "ti,j721e-uart", "ti,am654-uart";
538 clock-frequency = <48000000>;
539 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
540 clocks = <&k3_clks 284 2>;
541 clock-names = "fclk";
546 compatible = "ti,j721e-uart", "ti,am654-uart";
549 clock-frequency = <48000000>;
550 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
551 clocks = <&k3_clks 285 2>;
552 clock-names = "fclk";
557 compatible = "ti,j721e-uart", "ti,am654-uart";
560 clock-frequency = <48000000>;
561 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
562 clocks = <&k3_clks 286 2>;
563 clock-names = "fclk";
568 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
571 #address-cells = <1>;
572 #size-cells = <0>;
573 clock-names = "fck";
574 clocks = <&k3_clks 187 1>;
575 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
580 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
583 #address-cells = <1>;
584 #size-cells = <0>;
585 clock-names = "fck";
586 clocks = <&k3_clks 188 1>;
587 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
592 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
595 #address-cells = <1>;
596 #size-cells = <0>;
597 clock-names = "fck";
598 clocks = <&k3_clks 189 1>;
599 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
604 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
607 #address-cells = <1>;
608 #size-cells = <0>;
609 clock-names = "fck";
610 clocks = <&k3_clks 190 1>;
611 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
616 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
619 #address-cells = <1>;
620 #size-cells = <0>;
621 clock-names = "fck";
622 clocks = <&k3_clks 191 1>;
623 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
628 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
631 #address-cells = <1>;
632 #size-cells = <0>;
633 clock-names = "fck";
634 clocks = <&k3_clks 192 1>;
635 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
640 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
643 #address-cells = <1>;
644 #size-cells = <0>;
645 clock-names = "fck";
646 clocks = <&k3_clks 193 1>;
647 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
652 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
655 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
656 clock-names = "clk_ahb", "clk_xin";
657 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
658 ti,otap-del-sel-legacy = <0x0>;
659 ti,otap-del-sel-mmc-hs = <0x0>;
660 ti,otap-del-sel-ddr52 = <0x6>;
661 ti,otap-del-sel-hs200 = <0x8>;
662 ti,otap-del-sel-hs400 = <0x5>;
663 ti,itap-del-sel-legacy = <0x10>;
664 ti,itap-del-sel-mmc-hs = <0xa>;
665 ti,itap-del-sel-ddr52 = <0x3>;
666 ti,strobe-sel = <0x77>;
667 ti,clkbuf-sel = <0x7>;
668 ti,trm-icp = <0x8>;
669 bus-width = <8>;
670 mmc-ddr-1_8v;
671 mmc-hs200-1_8v;
672 mmc-hs400-1_8v;
673 dma-coherent;
678 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
681 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
682 clock-names = "clk_ahb", "clk_xin";
683 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
684 ti,otap-del-sel-legacy = <0x0>;
685 ti,otap-del-sel-sd-hs = <0x0>;
686 ti,otap-del-sel-sdr12 = <0xf>;
687 ti,otap-del-sel-sdr25 = <0xf>;
688 ti,otap-del-sel-sdr50 = <0xc>;
689 ti,otap-del-sel-sdr104 = <0x5>;
690 ti,otap-del-sel-ddr50 = <0xc>;
691 ti,itap-del-sel-legacy = <0x0>;
692 ti,itap-del-sel-sd-hs = <0x0>;
693 ti,itap-del-sel-sdr12 = <0x0>;
694 ti,itap-del-sel-sdr25 = <0x0>;
695 ti,clkbuf-sel = <0x7>;
696 ti,trm-icp = <0x8>;
697 dma-coherent;
702 compatible = "ti,j721e-wiz-10g";
703 #address-cells = <1>;
704 #size-cells = <1>;
705 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
706 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
707 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
708 num-lanes = <4>;
709 #reset-cells = <1>;
712 assigned-clocks = <&k3_clks 292 85>;
713 assigned-clock-parents = <&k3_clks 292 89>;
715 wiz0_pll0_refclk: pll0-refclk {
716 clocks = <&k3_clks 292 85>, <&serdes_refclk>;
717 clock-output-names = "wiz0_pll0_refclk";
718 #clock-cells = <0>;
719 assigned-clocks = <&wiz0_pll0_refclk>;
720 assigned-clock-parents = <&k3_clks 292 85>;
723 wiz0_pll1_refclk: pll1-refclk {
724 clocks = <&k3_clks 292 85>, <&serdes_refclk>;
725 clock-output-names = "wiz0_pll1_refclk";
726 #clock-cells = <0>;
727 assigned-clocks = <&wiz0_pll1_refclk>;
728 assigned-clock-parents = <&k3_clks 292 85>;
731 wiz0_refclk_dig: refclk-dig {
732 clocks = <&k3_clks 292 85>, <&serdes_refclk>;
733 clock-output-names = "wiz0_refclk_dig";
734 #clock-cells = <0>;
735 assigned-clocks = <&wiz0_refclk_dig>;
736 assigned-clock-parents = <&k3_clks 292 85>;
739 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
740 clocks = <&wiz0_refclk_dig>;
741 #clock-cells = <0>;
745 compatible = "ti,j721e-serdes-10g";
747 reg-names = "torrent_phy";
749 reset-names = "torrent_reset";
750 clocks = <&wiz0_pll0_refclk>;
751 clock-names = "refclk";
752 #address-cells = <1>;
753 #size-cells = <0>;
758 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
763 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
764 interrupt-names = "link_state";
767 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
768 max-link-speed = <3>;
769 num-lanes = <4>;
770 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
771 clocks = <&k3_clks 240 6>;
772 clock-names = "fck";
773 #address-cells = <3>;
774 #size-cells = <2>;
775 bus-range = <0x0 0xff>;
776 cdns,no-bar-match-nbits = <64>;
777 vendor-id = <0x104c>;
778 device-id = <0xb00f>;
779 msi-map = <0x0 &gic_its 0x0 0x10000>;
780 dma-coherent;
783 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
787 usbss0: cdns-usb@4104000 {
788 compatible = "ti,j721e-usb";
790 dma-coherent;
791 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
792 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
793 clock-names = "ref", "lpm";
794 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
795 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
796 #address-cells = <2>;
797 #size-cells = <2>;
805 reg-names = "otg", "xhci", "dev";
809 interrupt-names = "host",
812 maximum-speed = "super-speed";
814 cdns,phyrst-a-enable;
819 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
821 gpio-controller;
822 #gpio-cells = <2>;
823 interrupt-parent = <&main_gpio_intr>;
826 interrupt-controller;
827 #interrupt-cells = <2>;
829 ti,davinci-gpio-unbanked = <0>;
830 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
831 clocks = <&k3_clks 105 0>;
832 clock-names = "gpio";
837 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
839 gpio-controller;
840 #gpio-cells = <2>;
841 interrupt-parent = <&main_gpio_intr>;
844 interrupt-controller;
845 #interrupt-cells = <2>;
847 ti,davinci-gpio-unbanked = <0>;
848 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
849 clocks = <&k3_clks 107 0>;
850 clock-names = "gpio";
855 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
857 gpio-controller;
858 #gpio-cells = <2>;
859 interrupt-parent = <&main_gpio_intr>;
862 interrupt-controller;
863 #interrupt-cells = <2>;
865 ti,davinci-gpio-unbanked = <0>;
866 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
867 clocks = <&k3_clks 109 0>;
868 clock-names = "gpio";
873 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
875 gpio-controller;
876 #gpio-cells = <2>;
877 interrupt-parent = <&main_gpio_intr>;
880 interrupt-controller;
881 #interrupt-cells = <2>;
883 ti,davinci-gpio-unbanked = <0>;
884 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
885 clocks = <&k3_clks 111 0>;
886 clock-names = "gpio";
894 reg-names = "m_can", "message_ram";
895 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
896 clocks = <&k3_clks 156 0>, <&k3_clks 156 2>;
897 clock-names = "hclk", "cclk";
900 interrupt-names = "int0", "int1";
901 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
909 reg-names = "m_can", "message_ram";
910 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
911 clocks = <&k3_clks 158 0>, <&k3_clks 158 2>;
912 clock-names = "hclk", "cclk";
915 interrupt-names = "int0", "int1";
916 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
924 reg-names = "m_can", "message_ram";
925 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
926 clocks = <&k3_clks 160 0>, <&k3_clks 160 2>;
927 clock-names = "hclk", "cclk";
930 interrupt-names = "int0", "int1";
931 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
939 reg-names = "m_can", "message_ram";
940 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
941 clocks = <&k3_clks 161 0>, <&k3_clks 161 2>;
942 clock-names = "hclk", "cclk";
945 interrupt-names = "int0", "int1";
946 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
954 reg-names = "m_can", "message_ram";
955 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
956 clocks = <&k3_clks 162 0>, <&k3_clks 162 2>;
957 clock-names = "hclk", "cclk";
960 interrupt-names = "int0", "int1";
961 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
969 reg-names = "m_can", "message_ram";
970 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
971 clocks = <&k3_clks 163 0>, <&k3_clks 163 2>;
972 clock-names = "hclk", "cclk";
975 interrupt-names = "int0", "int1";
976 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
984 reg-names = "m_can", "message_ram";
985 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
986 clocks = <&k3_clks 164 0>, <&k3_clks 164 2>;
987 clock-names = "hclk", "cclk";
990 interrupt-names = "int0", "int1";
991 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
999 reg-names = "m_can", "message_ram";
1000 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
1001 clocks = <&k3_clks 165 0>, <&k3_clks 165 2>;
1002 clock-names = "hclk", "cclk";
1005 interrupt-names = "int0", "int1";
1006 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1014 reg-names = "m_can", "message_ram";
1015 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
1016 clocks = <&k3_clks 166 0>, <&k3_clks 166 2>;
1017 clock-names = "hclk", "cclk";
1020 interrupt-names = "int0", "int1";
1021 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1029 reg-names = "m_can", "message_ram";
1030 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
1031 clocks = <&k3_clks 167 0>, <&k3_clks 167 2>;
1032 clock-names = "hclk", "cclk";
1035 interrupt-names = "int0", "int1";
1036 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1044 reg-names = "m_can", "message_ram";
1045 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
1046 clocks = <&k3_clks 168 0>, <&k3_clks 168 2>;
1047 clock-names = "hclk", "cclk";
1050 interrupt-names = "int0", "int1";
1051 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1059 reg-names = "m_can", "message_ram";
1060 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
1061 clocks = <&k3_clks 169 0>, <&k3_clks 169 2>;
1062 clock-names = "hclk", "cclk";
1065 interrupt-names = "int0", "int1";
1066 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1074 reg-names = "m_can", "message_ram";
1075 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
1076 clocks = <&k3_clks 170 0>, <&k3_clks 170 2>;
1077 clock-names = "hclk", "cclk";
1080 interrupt-names = "int0", "int1";
1081 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1089 reg-names = "m_can", "message_ram";
1090 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
1091 clocks = <&k3_clks 171 0>, <&k3_clks 171 2>;
1092 clock-names = "hclk", "cclk";
1095 interrupt-names = "int0", "int1";
1096 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1104 reg-names = "m_can", "message_ram";
1105 power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
1106 clocks = <&k3_clks 150 0>, <&k3_clks 150 2>;
1107 clock-names = "hclk", "cclk";
1110 interrupt-names = "int0", "int1";
1111 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1119 reg-names = "m_can", "message_ram";
1120 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1121 clocks = <&k3_clks 151 0>, <&k3_clks 151 2>;
1122 clock-names = "hclk", "cclk";
1125 interrupt-names = "int0", "int1";
1126 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1134 reg-names = "m_can", "message_ram";
1135 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1136 clocks = <&k3_clks 152 0>, <&k3_clks 152 2>;
1137 clock-names = "hclk", "cclk";
1140 interrupt-names = "int0", "int1";
1141 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1149 reg-names = "m_can", "message_ram";
1150 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1151 clocks = <&k3_clks 153 0>, <&k3_clks 153 2>;
1152 clock-names = "hclk", "cclk";
1155 interrupt-names = "int0", "int1";
1156 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1161 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1166 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
1167 clocks = <&k3_clks 266 4>;
1172 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1177 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
1178 clocks = <&k3_clks 267 4>;
1183 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
1189 clocks = <&k3_clks 268 4>;
1194 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
1200 clocks = <&k3_clks 269 4>;
1205 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1208 #address-cells = <1>;
1209 #size-cells = <0>;
1210 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
1211 clocks = <&k3_clks 270 2>;
1216 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1221 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
1222 clocks = <&k3_clks 271 4>;
1227 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1230 #address-cells = <1>;
1231 #size-cells = <0>;
1232 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
1233 clocks = <&k3_clks 272 4>;
1238 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1243 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
1244 clocks = <&k3_clks 273 4>;
1249 compatible = "ti,j7-rti-wdt";
1251 clocks = <&k3_clks 252 1>;
1252 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1253 assigned-clocks = <&k3_clks 252 1>;
1254 assigned-clock-parents = <&k3_clks 252 5>;
1258 compatible = "ti,j7-rti-wdt";
1260 clocks = <&k3_clks 253 1>;
1261 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1262 assigned-clocks = <&k3_clks 253 1>;
1263 assigned-clock-parents = <&k3_clks 253 5>;
1267 compatible = "ti,am654-timer";
1270 clocks = <&k3_clks 49 1>;
1271 clock-names = "fck";
1272 assigned-clocks = <&k3_clks 49 1>;
1273 assigned-clock-parents = <&k3_clks 49 2>;
1274 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1275 ti,timer-pwm;
1279 compatible = "ti,am654-timer";
1282 clocks = <&k3_clks 50 1>;
1283 clock-names = "fck";
1284 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1285 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
1286 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1287 ti,timer-pwm;
1291 compatible = "ti,am654-timer";
1294 clocks = <&k3_clks 51 1>;
1295 clock-names = "fck";
1296 assigned-clocks = <&k3_clks 51 1>;
1297 assigned-clock-parents = <&k3_clks 51 2>;
1298 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1299 ti,timer-pwm;
1303 compatible = "ti,am654-timer";
1306 clocks = <&k3_clks 52 1>;
1307 clock-names = "fck";
1308 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1309 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
1310 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1311 ti,timer-pwm;
1315 compatible = "ti,am654-timer";
1318 clocks = <&k3_clks 53 1>;
1319 clock-names = "fck";
1320 assigned-clocks = <&k3_clks 53 1>;
1321 assigned-clock-parents = <&k3_clks 53 2>;
1322 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1323 ti,timer-pwm;
1327 compatible = "ti,am654-timer";
1330 clocks = <&k3_clks 54 1>;
1331 clock-names = "fck";
1332 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1333 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
1334 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1335 ti,timer-pwm;
1339 compatible = "ti,am654-timer";
1342 clocks = <&k3_clks 55 1>;
1343 clock-names = "fck";
1344 assigned-clocks = <&k3_clks 55 1>;
1345 assigned-clock-parents = <&k3_clks 55 2>;
1346 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1347 ti,timer-pwm;
1351 compatible = "ti,am654-timer";
1354 clocks = <&k3_clks 57 1>;
1355 clock-names = "fck";
1356 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1357 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
1358 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1359 ti,timer-pwm;
1363 compatible = "ti,am654-timer";
1366 clocks = <&k3_clks 58 1>;
1367 clock-names = "fck";
1368 assigned-clocks = <&k3_clks 58 1>;
1369 assigned-clock-parents = <&k3_clks 58 2>;
1370 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1371 ti,timer-pwm;
1375 compatible = "ti,am654-timer";
1378 clocks = <&k3_clks 59 1>;
1379 clock-names = "fck";
1380 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1381 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
1382 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1383 ti,timer-pwm;
1387 compatible = "ti,am654-timer";
1390 clocks = <&k3_clks 60 1>;
1391 clock-names = "fck";
1392 assigned-clocks = <&k3_clks 60 1>;
1393 assigned-clock-parents = <&k3_clks 60 2>;
1394 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1395 ti,timer-pwm;
1399 compatible = "ti,am654-timer";
1402 clocks = <&k3_clks 62 1>;
1403 clock-names = "fck";
1404 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1405 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
1406 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1407 ti,timer-pwm;
1411 compatible = "ti,am654-timer";
1414 clocks = <&k3_clks 63 1>;
1415 clock-names = "fck";
1416 assigned-clocks = <&k3_clks 63 1>;
1417 assigned-clock-parents = <&k3_clks 63 2>;
1418 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1419 ti,timer-pwm;
1423 compatible = "ti,am654-timer";
1426 clocks = <&k3_clks 64 1>;
1427 clock-names = "fck";
1428 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1429 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
1430 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1431 ti,timer-pwm;
1435 compatible = "ti,am654-timer";
1438 clocks = <&k3_clks 65 1>;
1439 clock-names = "fck";
1440 assigned-clocks = <&k3_clks 65 1>;
1441 assigned-clock-parents = <&k3_clks 65 2>;
1442 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1443 ti,timer-pwm;
1447 compatible = "ti,am654-timer";
1450 clocks = <&k3_clks 66 1>;
1451 clock-names = "fck";
1452 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1453 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
1454 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1455 ti,timer-pwm;
1459 compatible = "ti,am654-timer";
1462 clocks = <&k3_clks 67 1>;
1463 clock-names = "fck";
1464 assigned-clocks = <&k3_clks 67 1>;
1465 assigned-clock-parents = <&k3_clks 67 2>;
1466 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1467 ti,timer-pwm;
1471 compatible = "ti,am654-timer";
1474 clocks = <&k3_clks 68 1>;
1475 clock-names = "fck";
1476 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1477 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
1478 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1479 ti,timer-pwm;
1483 compatible = "ti,am654-timer";
1486 clocks = <&k3_clks 69 1>;
1487 clock-names = "fck";
1488 assigned-clocks = <&k3_clks 69 1>;
1489 assigned-clock-parents = <&k3_clks 69 2>;
1490 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1491 ti,timer-pwm;
1495 compatible = "ti,am654-timer";
1498 clocks = <&k3_clks 70 1>;
1499 clock-names = "fck";
1500 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1501 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
1502 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1503 ti,timer-pwm;
1507 compatible = "ti,j7200-r5fss";
1508 ti,cluster-mode = <1>;
1509 #address-cells = <1>;
1510 #size-cells = <1>;
1513 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1516 compatible = "ti,j7200-r5f";
1519 reg-names = "atcm", "btcm";
1521 ti,sci-dev-id = <245>;
1522 ti,sci-proc-ids = <0x06 0xff>;
1524 firmware-name = "j7200-main-r5f0_0-fw";
1525 ti,atcm-enable = <1>;
1526 ti,btcm-enable = <1>;
1531 compatible = "ti,j7200-r5f";
1534 reg-names = "atcm", "btcm";
1536 ti,sci-dev-id = <246>;
1537 ti,sci-proc-ids = <0x07 0xff>;
1539 firmware-name = "j7200-main-r5f0_1-fw";
1540 ti,atcm-enable = <1>;
1541 ti,btcm-enable = <1>;
1547 compatible = "ti,j721e-esm";
1549 bootph-pre-ram;
1550 ti,esm-pins = <656>, <657>;