Lines Matching +full:shared +full:- +full:dma +full:- +full:pool
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include "k3-j784s4.dtsi"
16 compatible = "ti,am69-sk", "ti,j784s4";
20 stdout-path = "serial2:115200n8";
36 bootph-all;
42 reserved_memory: reserved-memory {
43 #address-cells = <2>;
44 #size-cells = <2>;
49 no-map;
52 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
53 compatible = "shared-dma-pool";
55 no-map;
58 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
59 compatible = "shared-dma-pool";
61 no-map;
64 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
65 compatible = "shared-dma-pool";
67 no-map;
70 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
71 compatible = "shared-dma-pool";
73 no-map;
76 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
77 compatible = "shared-dma-pool";
79 no-map;
82 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
83 compatible = "shared-dma-pool";
85 no-map;
88 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
89 compatible = "shared-dma-pool";
91 no-map;
94 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
95 compatible = "shared-dma-pool";
97 no-map;
100 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
101 compatible = "shared-dma-pool";
103 no-map;
106 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
107 compatible = "shared-dma-pool";
109 no-map;
112 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
113 compatible = "shared-dma-pool";
115 no-map;
118 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
119 compatible = "shared-dma-pool";
121 no-map;
124 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
125 compatible = "shared-dma-pool";
127 no-map;
130 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
131 compatible = "shared-dma-pool";
133 no-map;
136 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
137 compatible = "shared-dma-pool";
139 no-map;
142 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
143 compatible = "shared-dma-pool";
145 no-map;
148 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
149 compatible = "shared-dma-pool";
151 no-map;
154 c71_0_memory_region: c71-memory@a8100000 {
155 compatible = "shared-dma-pool";
157 no-map;
160 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
161 compatible = "shared-dma-pool";
163 no-map;
166 c71_1_memory_region: c71-memory@a9100000 {
167 compatible = "shared-dma-pool";
169 no-map;
172 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
173 compatible = "shared-dma-pool";
175 no-map;
178 c71_2_memory_region: c71-memory@aa100000 {
179 compatible = "shared-dma-pool";
181 no-map;
184 c71_3_dma_memory_region: c71-dma-memory@ab000000 {
185 compatible = "shared-dma-pool";
187 no-map;
190 c71_3_memory_region: c71-memory@ab100000 {
191 compatible = "shared-dma-pool";
193 no-map;
197 vusb_main: regulator-vusb-main5v0 {
199 compatible = "regulator-fixed";
200 regulator-name = "vusb-main5v0";
201 regulator-min-microvolt = <5000000>;
202 regulator-max-microvolt = <5000000>;
203 regulator-always-on;
204 regulator-boot-on;
207 vsys_5v0: regulator-vsys5v0 {
209 compatible = "regulator-fixed";
210 regulator-name = "vsys_5v0";
211 regulator-min-microvolt = <5000000>;
212 regulator-max-microvolt = <5000000>;
213 vin-supply = <&vusb_main>;
214 regulator-always-on;
215 regulator-boot-on;
218 vsys_3v3: regulator-vsys3v3 {
220 compatible = "regulator-fixed";
221 regulator-name = "vsys_3v3";
222 regulator-min-microvolt = <3300000>;
223 regulator-max-microvolt = <3300000>;
224 vin-supply = <&vusb_main>;
225 regulator-always-on;
226 regulator-boot-on;
229 vdd_mmc1: regulator-sd {
231 compatible = "regulator-fixed";
232 regulator-name = "vdd_mmc1";
233 regulator-min-microvolt = <3300000>;
234 regulator-max-microvolt = <3300000>;
235 regulator-boot-on;
236 enable-active-high;
237 vin-supply = <&vsys_3v3>;
241 vdd_sd_dv: regulator-tlv71033 {
243 compatible = "regulator-gpio";
244 regulator-name = "tlv71033";
245 pinctrl-names = "default";
246 pinctrl-0 = <&vdd_sd_dv_pins_default>;
247 regulator-min-microvolt = <1800000>;
248 regulator-max-microvolt = <3300000>;
249 regulator-boot-on;
250 vin-supply = <&vsys_5v0>;
256 dp0_pwr_3v3: regulator-dp0-pwr {
257 compatible = "regulator-fixed";
258 regulator-name = "dp0-pwr";
259 regulator-min-microvolt = <3300000>;
260 regulator-max-microvolt = <3300000>;
261 pinctrl-names = "default";
262 pinctrl-0 = <&dp_pwr_en_pins_default>;
264 enable-active-high;
267 dp0: connector-dp0 {
268 compatible = "dp-connector";
270 type = "full-size";
271 dp-pwr-supply = <&dp0_pwr_3v3>;
275 remote-endpoint = <&dp0_out>;
280 connector-hdmi {
281 compatible = "hdmi-connector";
284 pinctrl-names = "default";
285 pinctrl-0 = <&hdmi_hpd_pins_default>;
286 ddc-i2c-bus = <&mcu_i2c1>;
287 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; /* HDMI_HPD */
291 remote-endpoint = <&tfp410_out>;
296 bridge-dvi {
298 pinctrl-names = "default";
299 pinctrl-0 = <&hdmi_pdn_pins_default>;
300 powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>; /* HDMI_PDn */
304 #address-cells = <1>;
305 #size-cells = <0>;
311 remote-endpoint = <&dpi1_out0>;
312 pclk-sample = <1>;
320 remote-endpoint = <&hdmi_connector_in>;
326 csi_mux: mux-controller {
327 compatible = "gpio-mux";
328 #mux-state-cells = <1>;
329 mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
330 idle-state = <0>;
333 transceiver1: can-phy0 {
335 #phy-cells = <0>;
336 max-bitrate = <5000000>;
339 transceiver2: can-phy1 {
341 #phy-cells = <0>;
342 max-bitrate = <5000000>;
345 transceiver3: can-phy2 {
347 #phy-cells = <0>;
348 max-bitrate = <5000000>;
351 transceiver4: can-phy3 {
353 #phy-cells = <0>;
354 max-bitrate = <5000000>;
360 bootph-all;
361 main_uart8_pins_default: main-uart8-default-pins {
362 bootph-all;
363 pinctrl-single,pins = <
369 main_i2c0_pins_default: main-i2c0-default-pins {
370 pinctrl-single,pins = <
376 main_i2c1_pins_default: main-i2c1-default-pins {
377 pinctrl-single,pins = <
383 main_mmc1_pins_default: main-mmc1-default-pins {
384 bootph-all;
385 pinctrl-single,pins = <
397 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
398 pinctrl-single,pins = <
403 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
404 pinctrl-single,pins = <
422 dp0_pins_default: dp0-default-pins {
423 pinctrl-single,pins = <
428 dp_pwr_en_pins_default: dp-pwr-en-default-pins {
429 pinctrl-single,pins = <
434 dss_vout0_pins_default: dss-vout0-default-pins {
435 pinctrl-single,pins = <
467 hdmi_hpd_pins_default: hdmi-hpd-default-pins {
468 pinctrl-single,pins = <
473 main_mcan6_pins_default: main-mcan6-default-pins {
474 pinctrl-single,pins = <
480 main_mcan7_pins_default: main-mcan7-default-pins {
481 pinctrl-single,pins = <
487 main_usbss0_pins_default: main-usbss0-default-pins {
488 pinctrl-single,pins = <
496 bootph-all;
497 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
498 pinctrl-single,pins = <
515 bootph-all;
516 pmic_irq_pins_default: pmic-irq-default-pins {
517 pinctrl-single,pins = <
523 wkup_uart0_pins_default: wkup-uart0-default-pins {
524 bootph-all;
525 pinctrl-single,pins = <
533 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
534 bootph-all;
535 pinctrl-single,pins = <
541 mcu_uart0_pins_default: mcu-uart0-default-pins {
542 bootph-all;
543 pinctrl-single,pins = <
549 mcu_i2c0_pins_default: mcu-i2c0-default-pins {
550 pinctrl-single,pins = <
556 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
557 pinctrl-single,pins = <
573 mcu_mdio_pins_default: mcu-mdio-default-pins {
574 pinctrl-single,pins = <
580 mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins {
581 pinctrl-single,pins = <
594 mcu_i2c1_pins_default: mcu-i2c1-default-pins {
595 pinctrl-single,pins = <
603 hdmi_pdn_pins_default: hdmi-pdn-default-pins {
604 pinctrl-single,pins = <
609 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
610 pinctrl-single,pins = <
616 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
617 pinctrl-single,pins = <
626 mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins {
627 pinctrl-single,pins = <
636 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
637 ti,mbox-rx = <0 0 0>;
638 ti,mbox-tx = <1 0 0>;
641 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
642 ti,mbox-rx = <2 0 0>;
643 ti,mbox-tx = <3 0 0>;
650 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
651 ti,mbox-rx = <0 0 0>;
652 ti,mbox-tx = <1 0 0>;
655 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
656 ti,mbox-rx = <2 0 0>;
657 ti,mbox-tx = <3 0 0>;
664 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
665 ti,mbox-rx = <0 0 0>;
666 ti,mbox-tx = <1 0 0>;
669 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
670 ti,mbox-rx = <2 0 0>;
671 ti,mbox-tx = <3 0 0>;
678 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
679 ti,mbox-rx = <0 0 0>;
680 ti,mbox-tx = <1 0 0>;
683 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
684 ti,mbox-rx = <2 0 0>;
685 ti,mbox-tx = <3 0 0>;
692 mbox_c71_0: mbox-c71-0 {
693 ti,mbox-rx = <0 0 0>;
694 ti,mbox-tx = <1 0 0>;
697 mbox_c71_1: mbox-c71-1 {
698 ti,mbox-rx = <2 0 0>;
699 ti,mbox-tx = <3 0 0>;
706 mbox_c71_2: mbox-c71-2 {
707 ti,mbox-rx = <0 0 0>;
708 ti,mbox-tx = <1 0 0>;
711 mbox_c71_3: mbox-c71-3 {
712 ti,mbox-rx = <2 0 0>;
713 ti,mbox-tx = <3 0 0>;
720 pinctrl-names = "default";
721 pinctrl-0 = <&wkup_uart0_pins_default>;
725 bootph-all;
727 pinctrl-names = "default";
728 pinctrl-0 = <&wkup_i2c0_pins_default>;
729 clock-frequency = <400000>;
732 /* AT24C512C-MAHM-T */
738 compatible = "ti,tps6594-q1";
740 system-power-controller;
741 pinctrl-names = "default";
742 pinctrl-0 = <&pmic_irq_pins_default>;
743 interrupt-parent = <&wkup_gpio0>;
745 gpio-controller;
746 #gpio-cells = <2>;
747 ti,primary-pmic;
748 buck12-supply = <&vsys_3v3>;
749 buck3-supply = <&vsys_3v3>;
750 buck4-supply = <&vsys_3v3>;
751 buck5-supply = <&vsys_3v3>;
752 ldo1-supply = <&vsys_3v3>;
753 ldo2-supply = <&vsys_3v3>;
754 ldo3-supply = <&vsys_3v3>;
755 ldo4-supply = <&vsys_3v3>;
759 regulator-name = "vdd_ddr_1v1";
760 regulator-min-microvolt = <1100000>;
761 regulator-max-microvolt = <1100000>;
762 regulator-boot-on;
763 regulator-always-on;
764 bootph-all;
768 regulator-name = "vdd_ram_0v85";
769 regulator-min-microvolt = <850000>;
770 regulator-max-microvolt = <850000>;
771 regulator-boot-on;
772 regulator-always-on;
773 bootph-all;
777 regulator-name = "vdd_io_1v8";
778 regulator-min-microvolt = <1800000>;
779 regulator-max-microvolt = <1800000>;
780 regulator-boot-on;
781 regulator-always-on;
782 bootph-all;
786 regulator-name = "vdd_mcu_0v85";
787 regulator-min-microvolt = <850000>;
788 regulator-max-microvolt = <850000>;
789 regulator-boot-on;
790 regulator-always-on;
791 bootph-all;
795 regulator-name = "vdd_mcuio_1v8";
796 regulator-min-microvolt = <1800000>;
797 regulator-max-microvolt = <1800000>;
798 regulator-boot-on;
799 regulator-always-on;
800 bootph-all;
804 regulator-name = "vdd_mcuio_3v3";
805 regulator-min-microvolt = <3300000>;
806 regulator-max-microvolt = <3300000>;
807 regulator-boot-on;
808 regulator-always-on;
809 bootph-all;
813 regulator-name = "vds_dll_0v8";
814 regulator-min-microvolt = <800000>;
815 regulator-max-microvolt = <800000>;
816 regulator-boot-on;
817 regulator-always-on;
818 bootph-all;
822 regulator-name = "vda_mcu_1v8";
823 regulator-min-microvolt = <1800000>;
824 regulator-max-microvolt = <1800000>;
825 regulator-boot-on;
826 regulator-always-on;
827 bootph-all;
835 bootph-pre-ram;
836 regulator-name = "VDD_CPU_AVS";
837 regulator-min-microvolt = <600000>;
838 regulator-max-microvolt = <900000>;
839 regulator-boot-on;
840 regulator-always-on;
846 regulator-name = "VDD_CORE_0V8";
847 regulator-min-microvolt = <760000>;
848 regulator-max-microvolt = <840000>;
849 regulator-boot-on;
850 regulator-always-on;
856 pinctrl-names = "default";
857 pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>;
861 bootph-all;
863 pinctrl-names = "default";
864 pinctrl-0 = <&mcu_uart0_pins_default>;
869 pinctrl-names = "default";
870 pinctrl-0 = <&mcu_i2c0_pins_default>;
871 clock-frequency = <400000>;
875 bootph-all;
877 pinctrl-names = "default";
878 pinctrl-0 = <&main_uart8_pins_default>;
883 pinctrl-names = "default";
884 pinctrl-0 = <&main_i2c0_pins_default>;
885 clock-frequency = <400000>;
890 gpio-controller;
891 #gpio-cells = <2>;
892 gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
902 pinctrl-names = "default";
903 pinctrl-0 = <&main_i2c1_pins_default>;
904 clock-frequency = <400000>;
910 gpio-controller;
911 #gpio-cells = <2>;
912 gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz",
916 i2c-mux@70 {
918 #address-cells = <1>;
919 #size-cells = <0>;
923 #address-cells = <1>;
924 #size-cells = <0>;
929 #address-cells = <1>;
930 #size-cells = <0>;
938 bootph-all;
941 non-removable;
942 ti,driver-strength-ohm = <50>;
943 disable-wp;
947 bootph-all;
950 pinctrl-0 = <&main_mmc1_pins_default>;
951 pinctrl-names = "default";
952 disable-wp;
953 vmmc-supply = <&vdd_mmc1>;
954 vqmmc-supply = <&vdd_sd_dv>;
959 pinctrl-names = "default";
960 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
965 pinctrl-names = "default";
966 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
970 mcu_phy0: ethernet-phy@0 {
972 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
973 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
974 ti,min-output-impedance;
980 phy-mode = "rgmii-rxid";
981 phy-handle = <&mcu_phy0>;
986 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
992 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
997 ti,cluster-mode = <0>;
1001 ti,cluster-mode = <0>;
1046 ti,cluster-mode = <0>;
1051 memory-region = <&main_r5fss0_core0_dma_memory_region>,
1057 memory-region = <&main_r5fss0_core1_dma_memory_region>,
1063 memory-region = <&main_r5fss1_core0_dma_memory_region>,
1069 memory-region = <&main_r5fss1_core1_dma_memory_region>,
1075 memory-region = <&main_r5fss2_core0_dma_memory_region>,
1081 memory-region = <&main_r5fss2_core1_dma_memory_region>,
1088 memory-region = <&c71_0_dma_memory_region>,
1095 memory-region = <&c71_1_dma_memory_region>,
1102 memory-region = <&c71_2_dma_memory_region>,
1109 memory-region = <&c71_3_dma_memory_region>,
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&mcu_i2c1_pins_default>;
1121 clock-frequency = <100000>;
1126 clock-frequency = <100000000>;
1131 pinctrl-names = "default";
1132 pinctrl-0 = <&dss_vout0_pins_default>;
1133 assigned-clocks = <&k3_clks 218 2>,
1135 assigned-clock-parents = <&k3_clks 218 3>,
1147 cdns,num-lanes = <4>;
1148 #phy-cells = <0>;
1149 cdns,phy-type = <PHY_TYPE_DP>;
1157 pinctrl-names = "default";
1158 pinctrl-0 = <&dp0_pins_default>;
1160 phy-names = "dpphy";
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1172 remote-endpoint = <&dp0_in>;
1181 remote-endpoint = <&tfp410_in>;
1192 remote-endpoint = <&dpi0_out>;
1200 remote-endpoint = <&dp0_connector_in>;
1207 pinctrl-names = "default";
1208 pinctrl-0 = <&mcu_mcan0_pins_default>;
1214 pinctrl-names = "default";
1215 pinctrl-0 = <&mcu_mcan1_pins_default>;
1221 pinctrl-names = "default";
1222 pinctrl-0 = <&main_mcan6_pins_default>;
1228 pinctrl-names = "default";
1229 pinctrl-0 = <&main_mcan7_pins_default>;
1235 pinctrl-names = "default";
1236 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
1239 compatible = "jedec,spi-nor";
1241 spi-tx-bus-width = <8>;
1242 spi-rx-bus-width = <8>;
1243 spi-max-frequency = <25000000>;
1244 cdns,tshsl-ns = <60>;
1245 cdns,tsd2d-ns = <60>;
1246 cdns,tchsh-ns = <60>;
1247 cdns,tslch-ns = <60>;
1248 cdns,read-delay = <4>;
1251 bootph-all;
1252 compatible = "fixed-partitions";
1253 #address-cells = <1>;
1254 #size-cells = <1>;
1267 label = "ospi.u-boot";
1287 bootph-pre-ram;
1296 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
1311 cdns,num-lanes = <3>;
1312 #phy-cells = <0>;
1313 cdns,phy-type = <PHY_TYPE_PCIE>;
1319 cdns,num-lanes = <1>;
1320 #phy-cells = <0>;
1321 cdns,phy-type = <PHY_TYPE_USB3>;
1335 cdns,num-lanes = <4>;
1336 #phy-cells = <0>;
1337 cdns,phy-type = <PHY_TYPE_PCIE>;
1344 reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>;
1346 phy-names = "pcie-phy";
1351 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
1353 phy-names = "pcie-phy";
1354 num-lanes = <2>;
1359 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
1361 phy-names = "pcie-phy";
1362 num-lanes = <1>;
1366 idle-states = <0>; /* USB0 to SERDES0 */
1371 pinctrl-0 = <&main_usbss0_pins_default>;
1372 pinctrl-names = "default";
1373 ti,vbus-divider;
1379 maximum-speed = "super-speed";
1381 phy-names = "cdns3,usb3-phy";