Lines Matching +full:opp +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
4 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include "k3-am62p.dtsi"
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu-map {
39 compatible = "arm,cortex-a53";
42 enable-method = "psci";
43 i-cache-size = <0x8000>;
44 i-cache-line-size = <64>;
45 i-cache-sets = <256>;
46 d-cache-size = <0x8000>;
47 d-cache-line-size = <64>;
48 d-cache-sets = <128>;
49 next-level-cache = <&l2_0>;
50 operating-points-v2 = <&a53_opp_table>;
55 compatible = "arm,cortex-a53";
58 enable-method = "psci";
59 i-cache-size = <0x8000>;
60 i-cache-line-size = <64>;
61 i-cache-sets = <256>;
62 d-cache-size = <0x8000>;
63 d-cache-line-size = <64>;
64 d-cache-sets = <128>;
65 next-level-cache = <&l2_0>;
66 operating-points-v2 = <&a53_opp_table>;
71 compatible = "arm,cortex-a53";
74 enable-method = "psci";
75 i-cache-size = <0x8000>;
76 i-cache-line-size = <64>;
77 i-cache-sets = <256>;
78 d-cache-size = <0x8000>;
79 d-cache-line-size = <64>;
80 d-cache-sets = <128>;
81 next-level-cache = <&l2_0>;
82 operating-points-v2 = <&a53_opp_table>;
87 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 i-cache-size = <0x8000>;
92 i-cache-line-size = <64>;
93 i-cache-sets = <256>;
94 d-cache-size = <0x8000>;
95 d-cache-line-size = <64>;
96 d-cache-sets = <128>;
97 next-level-cache = <&l2_0>;
98 operating-points-v2 = <&a53_opp_table>;
103 a53_opp_table: opp-table {
104 compatible = "operating-points-v2-ti-cpu";
105 opp-shared;
108 opp-200000000 {
109 opp-hz = /bits/ 64 <200000000>;
110 opp-supported-hw = <0x01 0x0007>;
111 clock-latency-ns = <6000000>;
114 opp-400000000 {
115 opp-hz = /bits/ 64 <400000000>;
116 opp-supported-hw = <0x01 0x0007>;
117 clock-latency-ns = <6000000>;
120 opp-600000000 {
121 opp-hz = /bits/ 64 <600000000>;
122 opp-supported-hw = <0x01 0x0007>;
123 clock-latency-ns = <6000000>;
126 opp-800000000 {
127 opp-hz = /bits/ 64 <800000000>;
128 opp-supported-hw = <0x01 0x0007>;
129 clock-latency-ns = <6000000>;
132 opp-1000000000 {
133 opp-hz = /bits/ 64 <1000000000>;
134 opp-supported-hw = <0x01 0x0006>;
135 clock-latency-ns = <6000000>;
138 opp-1250000000 {
139 opp-hz = /bits/ 64 <1250000000>;
140 opp-supported-hw = <0x01 0x0004>;
141 clock-latency-ns = <6000000>;
142 opp-suspend;
146 l2_0: l2-cache0 {
148 cache-unified;
149 cache-level = <2>;
150 cache-size = <0x80000>;
151 cache-line-size = <64>;
152 cache-sets = <512>;