Lines Matching +full:interrupt +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk3588-base.dtsi"
7 #include "rk3588-extra-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
16 clock-names = "ref_clk", "suspend_clk", "bus_clk";
19 phy-names = "usb2-phy", "usb3-phy";
21 power-domains = <&power RK3588_PD_USB>;
24 snps,dis-u2-freeclk-exists-quirk;
25 snps,dis-del-phy-power-chg-quirk;
26 snps,dis-tx-ipgap-linecheck-quirk;
31 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
36 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
41 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
46 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
48 #address-cells = <1>;
49 #size-cells = <1>;
52 compatible = "rockchip,rk3588-usb2phy";
54 #clock-cells = <0>;
56 clock-names = "phyclk";
57 clock-output-names = "usb480m_phy1";
60 reset-names = "phy", "apb";
63 u2phy1_otg: otg-port {
64 #phy-cells = <0>;
71 compatible = "rockchip,rk3588-i2s-tdm";
75 clock-names = "mclk_tx", "mclk_rx", "hclk";
76 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
77 assigned-clock-parents = <&cru PLL_AUPLL>;
79 dma-names = "tx";
80 power-domains = <&power RK3588_PD_VO0>;
82 reset-names = "tx-m";
83 #sound-dai-cells = <0>;
88 compatible = "rockchip,rk3588-i2s-tdm";
92 clock-names = "mclk_tx", "mclk_rx", "hclk";
93 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
94 assigned-clock-parents = <&cru PLL_AUPLL>;
96 dma-names = "tx";
97 power-domains = <&power RK3588_PD_VO1>;
99 reset-names = "tx-m";
100 #sound-dai-cells = <0>;
105 compatible = "rockchip,rk3588-i2s-tdm";
109 clock-names = "mclk_tx", "mclk_rx", "hclk";
110 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
111 assigned-clock-parents = <&cru PLL_AUPLL>;
113 dma-names = "rx";
114 power-domains = <&power RK3588_PD_VO1>;
116 reset-names = "rx-m";
117 #sound-dai-cells = <0>;
122 compatible = "rockchip,rk3588-i2s-tdm";
126 clock-names = "mclk_tx", "mclk_rx", "hclk";
127 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
128 assigned-clock-parents = <&cru PLL_AUPLL>;
130 dma-names = "rx";
131 power-domains = <&power RK3588_PD_VO1>;
133 reset-names = "rx-m";
134 #sound-dai-cells = <0>;
139 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
140 #address-cells = <3>;
141 #size-cells = <2>;
142 bus-range = <0x00 0x0f>;
146 clock-names = "aclk_mst", "aclk_slv",
155 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
156 #interrupt-cells = <1>;
157 interrupt-map-mask = <0 0 0 7>;
158 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
162 linux,pci-domain = <0>;
163 max-link-speed = <3>;
164 msi-map = <0x0000 &its1 0x0000 0x1000>;
165 iommu-map = <0x0000 &mmu600_pcie 0x0000 0x1000>;
166 num-lanes = <4>;
168 phy-names = "pcie-phy";
169 power-domains = <&power RK3588_PD_PCIE>;
176 reg-names = "dbi", "apb", "config";
178 reset-names = "pwr", "pipe";
181 pcie3x4_intc: legacy-interrupt-controller {
182 interrupt-controller;
183 #address-cells = <0>;
184 #interrupt-cells = <1>;
185 interrupt-parent = <&gic>;
190 pcie3x4_ep: pcie-ep@fe150000 {
191 compatible = "rockchip,rk3588-pcie-ep";
197 reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
201 clock-names = "aclk_mst", "aclk_slv",
213 interrupt-names = "sys", "pmc", "msg", "legacy", "err",
215 max-link-speed = <3>;
216 num-lanes = <4>;
218 phy-names = "pcie-phy";
219 power-domains = <&power RK3588_PD_PCIE>;
221 reset-names = "pwr", "pipe";
226 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
227 #address-cells = <3>;
228 #size-cells = <2>;
229 bus-range = <0x10 0x1f>;
233 clock-names = "aclk_mst", "aclk_slv",
242 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
243 #interrupt-cells = <1>;
244 interrupt-map-mask = <0 0 0 7>;
245 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
249 linux,pci-domain = <1>;
250 max-link-speed = <3>;
251 msi-map = <0x1000 &its1 0x1000 0x1000>;
252 iommu-map = <0x1000 &mmu600_pcie 0x1000 0x1000>;
253 num-lanes = <2>;
255 phy-names = "pcie-phy";
256 power-domains = <&power RK3588_PD_PCIE>;
263 reg-names = "dbi", "apb", "config";
265 reset-names = "pwr", "pipe";
268 pcie3x2_intc: legacy-interrupt-controller {
269 interrupt-controller;
270 #address-cells = <0>;
271 #interrupt-cells = <1>;
272 interrupt-parent = <&gic>;
278 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
279 bus-range = <0x20 0x2f>;
283 clock-names = "aclk_mst", "aclk_slv",
292 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
293 #interrupt-cells = <1>;
294 interrupt-map-mask = <0 0 0 7>;
295 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
299 linux,pci-domain = <2>;
300 max-link-speed = <2>;
301 msi-map = <0x2000 &its0 0x2000 0x1000>;
302 iommu-map = <0x2000 &mmu600_pcie 0x2000 0x1000>;
303 num-lanes = <1>;
305 phy-names = "pcie-phy";
306 power-domains = <&power RK3588_PD_PCIE>;
313 reg-names = "dbi", "apb", "config";
315 reset-names = "pwr", "pipe";
316 #address-cells = <3>;
317 #size-cells = <2>;
320 pcie2x1l0_intc: legacy-interrupt-controller {
321 interrupt-controller;
322 #address-cells = <0>;
323 #interrupt-cells = <1>;
324 interrupt-parent = <&gic>;
330 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
334 interrupt-names = "macirq", "eth_wake_irq";
338 clock-names = "stmmaceth", "clk_mac_ref",
341 power-domains = <&power RK3588_PD_GMAC>;
343 reset-names = "stmmaceth";
345 rockchip,php-grf = <&php_grf>;
346 snps,axi-config = <&gmac0_stmmac_axi_setup>;
347 snps,mixed-burst;
348 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
349 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
354 compatible = "snps,dwmac-mdio";
355 #address-cells = <0x1>;
356 #size-cells = <0x0>;
359 gmac0_stmmac_axi_setup: stmmac-axi-config {
365 gmac0_mtl_rx_setup: rx-queues-config {
366 snps,rx-queues-to-use = <2>;
371 gmac0_mtl_tx_setup: tx-queues-config {
372 snps,tx-queues-to-use = <2>;
379 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
385 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
386 ports-implemented = <0x1>;
387 #address-cells = <1>;
388 #size-cells = <0>;
391 sata-port@0 {
393 hba-port-cap = <HBA_PORT_FBSCP>;
395 phy-names = "sata-phy";
396 snps,rx-ts-max = <32>;
397 snps,tx-ts-max = <32>;
402 compatible = "rockchip,rk3588-usbdp-phy";
404 #phy-cells = <1>;
409 clock-names = "refclk", "immortal", "pclk", "utmi";
415 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
416 rockchip,u2phy-grf = <&usb2phy1_grf>;
417 rockchip,usb-grf = <&usb_grf>;
418 rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
419 rockchip,vo-grf = <&vo0_grf>;
424 compatible = "rockchip,rk3588-naneng-combphy";
428 clock-names = "ref", "apb", "pipe";
429 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
430 assigned-clock-rates = <100000000>;
431 #phy-cells = <1>;
433 reset-names = "phy", "apb";
434 rockchip,pipe-grf = <&php_grf>;
435 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
440 compatible = "rockchip,rk3588-pcie3-phy";
442 #phy-cells = <0>;
444 clock-names = "pclk";
446 reset-names = "phy";
447 rockchip,pipe-grf = <&php_grf>;
448 rockchip,phy-grf = <&pcie30_phy_grf>;