Lines Matching +full:rk3288 +full:- +full:vpu
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
55 #address-cells = <1>;
56 #size-cells = <0>;
58 cpu-map {
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 capacity-dmips-mhz = <530>;
98 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
99 assigned-clock-rates = <816000000>;
100 cpu-idle-states = <&CPU_SLEEP>;
101 i-cache-size = <32768>;
102 i-cache-line-size = <64>;
103 i-cache-sets = <128>;
104 d-cache-size = <32768>;
105 d-cache-line-size = <64>;
106 d-cache-sets = <128>;
107 next-level-cache = <&l2_cache_l0>;
108 dynamic-power-coefficient = <228>;
109 #cooling-cells = <2>;
114 compatible = "arm,cortex-a55";
116 enable-method = "psci";
117 capacity-dmips-mhz = <530>;
119 cpu-idle-states = <&CPU_SLEEP>;
120 i-cache-size = <32768>;
121 i-cache-line-size = <64>;
122 i-cache-sets = <128>;
123 d-cache-size = <32768>;
124 d-cache-line-size = <64>;
125 d-cache-sets = <128>;
126 next-level-cache = <&l2_cache_l1>;
127 dynamic-power-coefficient = <228>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a55";
135 enable-method = "psci";
136 capacity-dmips-mhz = <530>;
138 cpu-idle-states = <&CPU_SLEEP>;
139 i-cache-size = <32768>;
140 i-cache-line-size = <64>;
141 i-cache-sets = <128>;
142 d-cache-size = <32768>;
143 d-cache-line-size = <64>;
144 d-cache-sets = <128>;
145 next-level-cache = <&l2_cache_l2>;
146 dynamic-power-coefficient = <228>;
147 #cooling-cells = <2>;
152 compatible = "arm,cortex-a55";
154 enable-method = "psci";
155 capacity-dmips-mhz = <530>;
157 cpu-idle-states = <&CPU_SLEEP>;
158 i-cache-size = <32768>;
159 i-cache-line-size = <64>;
160 i-cache-sets = <128>;
161 d-cache-size = <32768>;
162 d-cache-line-size = <64>;
163 d-cache-sets = <128>;
164 next-level-cache = <&l2_cache_l3>;
165 dynamic-power-coefficient = <228>;
166 #cooling-cells = <2>;
171 compatible = "arm,cortex-a76";
173 enable-method = "psci";
174 capacity-dmips-mhz = <1024>;
176 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
177 assigned-clock-rates = <816000000>;
178 cpu-idle-states = <&CPU_SLEEP>;
179 i-cache-size = <65536>;
180 i-cache-line-size = <64>;
181 i-cache-sets = <256>;
182 d-cache-size = <65536>;
183 d-cache-line-size = <64>;
184 d-cache-sets = <256>;
185 next-level-cache = <&l2_cache_b0>;
186 dynamic-power-coefficient = <416>;
187 #cooling-cells = <2>;
192 compatible = "arm,cortex-a76";
194 enable-method = "psci";
195 capacity-dmips-mhz = <1024>;
197 cpu-idle-states = <&CPU_SLEEP>;
198 i-cache-size = <65536>;
199 i-cache-line-size = <64>;
200 i-cache-sets = <256>;
201 d-cache-size = <65536>;
202 d-cache-line-size = <64>;
203 d-cache-sets = <256>;
204 next-level-cache = <&l2_cache_b1>;
205 dynamic-power-coefficient = <416>;
206 #cooling-cells = <2>;
211 compatible = "arm,cortex-a76";
213 enable-method = "psci";
214 capacity-dmips-mhz = <1024>;
216 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
217 assigned-clock-rates = <816000000>;
218 cpu-idle-states = <&CPU_SLEEP>;
219 i-cache-size = <65536>;
220 i-cache-line-size = <64>;
221 i-cache-sets = <256>;
222 d-cache-size = <65536>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <256>;
225 next-level-cache = <&l2_cache_b2>;
226 dynamic-power-coefficient = <416>;
227 #cooling-cells = <2>;
232 compatible = "arm,cortex-a76";
234 enable-method = "psci";
235 capacity-dmips-mhz = <1024>;
237 cpu-idle-states = <&CPU_SLEEP>;
238 i-cache-size = <65536>;
239 i-cache-line-size = <64>;
240 i-cache-sets = <256>;
241 d-cache-size = <65536>;
242 d-cache-line-size = <64>;
243 d-cache-sets = <256>;
244 next-level-cache = <&l2_cache_b3>;
245 dynamic-power-coefficient = <416>;
246 #cooling-cells = <2>;
249 idle-states {
250 entry-method = "psci";
251 CPU_SLEEP: cpu-sleep {
252 compatible = "arm,idle-state";
253 local-timer-stop;
254 arm,psci-suspend-param = <0x0010000>;
255 entry-latency-us = <100>;
256 exit-latency-us = <120>;
257 min-residency-us = <1000>;
261 l2_cache_l0: l2-cache-l0 {
263 cache-size = <131072>;
264 cache-line-size = <64>;
265 cache-sets = <512>;
266 cache-level = <2>;
267 cache-unified;
268 next-level-cache = <&l3_cache>;
271 l2_cache_l1: l2-cache-l1 {
273 cache-size = <131072>;
274 cache-line-size = <64>;
275 cache-sets = <512>;
276 cache-level = <2>;
277 cache-unified;
278 next-level-cache = <&l3_cache>;
281 l2_cache_l2: l2-cache-l2 {
283 cache-size = <131072>;
284 cache-line-size = <64>;
285 cache-sets = <512>;
286 cache-level = <2>;
287 cache-unified;
288 next-level-cache = <&l3_cache>;
291 l2_cache_l3: l2-cache-l3 {
293 cache-size = <131072>;
294 cache-line-size = <64>;
295 cache-sets = <512>;
296 cache-level = <2>;
297 cache-unified;
298 next-level-cache = <&l3_cache>;
301 l2_cache_b0: l2-cache-b0 {
303 cache-size = <524288>;
304 cache-line-size = <64>;
305 cache-sets = <1024>;
306 cache-level = <2>;
307 cache-unified;
308 next-level-cache = <&l3_cache>;
311 l2_cache_b1: l2-cache-b1 {
313 cache-size = <524288>;
314 cache-line-size = <64>;
315 cache-sets = <1024>;
316 cache-level = <2>;
317 cache-unified;
318 next-level-cache = <&l3_cache>;
321 l2_cache_b2: l2-cache-b2 {
323 cache-size = <524288>;
324 cache-line-size = <64>;
325 cache-sets = <1024>;
326 cache-level = <2>;
327 cache-unified;
328 next-level-cache = <&l3_cache>;
331 l2_cache_b3: l2-cache-b3 {
333 cache-size = <524288>;
334 cache-line-size = <64>;
335 cache-sets = <1024>;
336 cache-level = <2>;
337 cache-unified;
338 next-level-cache = <&l3_cache>;
346 l3_cache: l3-cache {
348 cache-size = <3145728>;
349 cache-line-size = <64>;
350 cache-sets = <4096>;
351 cache-level = <3>;
352 cache-unified;
355 display_subsystem: display-subsystem {
356 compatible = "rockchip,display-subsystem";
362 compatible = "linaro,optee-tz";
367 compatible = "arm,scmi-smc";
368 arm,smc-id = <0x82000010>;
370 #address-cells = <1>;
371 #size-cells = <0>;
375 #clock-cells = <1>;
380 #reset-cells = <1>;
385 pmu-a55 {
386 compatible = "arm,cortex-a55-pmu";
390 pmu-a76 {
391 compatible = "arm,cortex-a76-pmu";
396 compatible = "arm,psci-1.0";
400 spll: clock-0 {
401 compatible = "fixed-clock";
402 clock-frequency = <702000000>;
403 clock-output-names = "spll";
404 #clock-cells = <0>;
408 compatible = "arm,armv8-timer";
414 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
417 xin24m: clock-1 {
418 compatible = "fixed-clock";
419 clock-frequency = <24000000>;
420 clock-output-names = "xin24m";
421 #clock-cells = <0>;
424 xin32k: clock-2 {
425 compatible = "fixed-clock";
426 clock-frequency = <32768>;
427 clock-output-names = "xin32k";
428 #clock-cells = <0>;
432 compatible = "mmio-sram";
435 #address-cells = <1>;
436 #size-cells = <1>;
439 compatible = "arm,scmi-shmem";
445 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
447 #cooling-cells = <2>;
448 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
449 assigned-clock-rates = <200000000>;
452 clock-names = "core", "coregroup", "stacks";
453 dynamic-power-coefficient = <2982>;
457 interrupt-names = "job", "mmu", "gpu";
458 power-domains = <&power RK3588_PD_GPU>;
463 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
468 clock-names = "ref_clk", "suspend_clk", "bus_clk";
471 phy-names = "usb2-phy", "usb3-phy";
473 power-domains = <&power RK3588_PD_USB>;
476 snps,dis-u1-entry-quirk;
477 snps,dis-u2-entry-quirk;
478 snps,dis-u2-freeclk-exists-quirk;
479 snps,dis-del-phy-power-chg-quirk;
480 snps,dis-tx-ipgap-linecheck-quirk;
485 compatible = "rockchip,rk3588-ehci", "generic-ehci";
490 phy-names = "usb";
491 power-domains = <&power RK3588_PD_USB>;
496 compatible = "rockchip,rk3588-ohci", "generic-ohci";
501 phy-names = "usb";
502 power-domains = <&power RK3588_PD_USB>;
507 compatible = "rockchip,rk3588-ehci", "generic-ehci";
512 phy-names = "usb";
513 power-domains = <&power RK3588_PD_USB>;
518 compatible = "rockchip,rk3588-ohci", "generic-ohci";
523 phy-names = "usb";
524 power-domains = <&power RK3588_PD_USB>;
529 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
535 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
538 phy-names = "usb3-phy";
542 snps,dis-u2-freeclk-exists-quirk;
543 snps,dis-del-phy-power-chg-quirk;
544 snps,dis-tx-ipgap-linecheck-quirk;
550 compatible = "arm,smmu-v3";
556 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
557 #iommu-cells = <1>;
561 compatible = "arm,smmu-v3";
567 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
568 #iommu-cells = <1>;
573 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
578 compatible = "rockchip,rk3588-sys-grf", "syscon";
583 compatible = "rockchip,rk3588-vop-grf", "syscon";
588 compatible = "rockchip,rk3588-vo0-grf", "syscon";
594 compatible = "rockchip,rk3588-vo1-grf", "syscon";
600 compatible = "rockchip,rk3588-usb-grf", "syscon";
605 compatible = "rockchip,rk3588-php-grf", "syscon";
610 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
615 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
620 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
625 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
627 #address-cells = <1>;
628 #size-cells = <1>;
631 compatible = "rockchip,rk3588-usb2phy";
633 #clock-cells = <0>;
635 clock-names = "phyclk";
636 clock-output-names = "usb480m_phy0";
639 reset-names = "phy", "apb";
642 u2phy0_otg: otg-port {
643 #phy-cells = <0>;
650 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
652 #address-cells = <1>;
653 #size-cells = <1>;
656 compatible = "rockchip,rk3588-usb2phy";
658 #clock-cells = <0>;
660 clock-names = "phyclk";
661 clock-output-names = "usb480m_phy2";
664 reset-names = "phy", "apb";
667 u2phy2_host: host-port {
668 #phy-cells = <0>;
675 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
677 #address-cells = <1>;
678 #size-cells = <1>;
681 compatible = "rockchip,rk3588-usb2phy";
683 #clock-cells = <0>;
685 clock-names = "phyclk";
686 clock-output-names = "usb480m_phy3";
689 reset-names = "phy", "apb";
692 u2phy3_host: host-port {
693 #phy-cells = <0>;
700 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
705 compatible = "rockchip,rk3588-ioc", "syscon";
710 compatible = "mmio-sram";
713 #address-cells = <1>;
714 #size-cells = <1>;
717 cru: clock-controller@fd7c0000 {
718 compatible = "rockchip,rk3588-cru";
720 assigned-clocks =
730 assigned-clock-rates =
741 #clock-cells = <1>;
742 #reset-cells = <1>;
746 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
750 clock-names = "i2c", "pclk";
751 pinctrl-0 = <&i2c0m0_xfer>;
752 pinctrl-names = "default";
753 #address-cells = <1>;
754 #size-cells = <0>;
759 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
763 clock-names = "baudclk", "apb_pclk";
765 dma-names = "tx", "rx";
766 pinctrl-0 = <&uart0m1_xfer>;
767 pinctrl-names = "default";
768 reg-shift = <2>;
769 reg-io-width = <4>;
774 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
777 clock-names = "pwm", "pclk";
778 pinctrl-0 = <&pwm0m0_pins>;
779 pinctrl-names = "default";
780 #pwm-cells = <3>;
785 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
788 clock-names = "pwm", "pclk";
789 pinctrl-0 = <&pwm1m0_pins>;
790 pinctrl-names = "default";
791 #pwm-cells = <3>;
796 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
799 clock-names = "pwm", "pclk";
800 pinctrl-0 = <&pwm2m0_pins>;
801 pinctrl-names = "default";
802 #pwm-cells = <3>;
807 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
810 clock-names = "pwm", "pclk";
811 pinctrl-0 = <&pwm3m0_pins>;
812 pinctrl-names = "default";
813 #pwm-cells = <3>;
817 pmu: power-management@fd8d8000 {
818 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
821 power: power-controller {
822 compatible = "rockchip,rk3588-power-controller";
823 #address-cells = <1>;
824 #power-domain-cells = <1>;
825 #size-cells = <0>;
829 power-domain@RK3588_PD_NPU {
831 #power-domain-cells = <0>;
832 #address-cells = <1>;
833 #size-cells = <0>;
835 power-domain@RK3588_PD_NPUTOP {
844 #power-domain-cells = <0>;
845 #address-cells = <1>;
846 #size-cells = <0>;
848 power-domain@RK3588_PD_NPU1 {
854 #power-domain-cells = <0>;
856 power-domain@RK3588_PD_NPU2 {
862 #power-domain-cells = <0>;
867 power-domain@RK3588_PD_GPU {
876 #power-domain-cells = <0>;
879 power-domain@RK3588_PD_VCODEC {
881 #address-cells = <1>;
882 #size-cells = <0>;
883 #power-domain-cells = <0>;
885 power-domain@RK3588_PD_RKVDEC0 {
893 #power-domain-cells = <0>;
895 power-domain@RK3588_PD_RKVDEC1 {
902 #power-domain-cells = <0>;
904 power-domain@RK3588_PD_VENC0 {
911 #address-cells = <1>;
912 #size-cells = <0>;
913 #power-domain-cells = <0>;
915 power-domain@RK3588_PD_VENC1 {
924 #power-domain-cells = <0>;
929 power-domain@RK3588_PD_VDPU {
957 #address-cells = <1>;
958 #size-cells = <0>;
959 #power-domain-cells = <0>;
962 power-domain@RK3588_PD_AV1 {
968 #power-domain-cells = <0>;
970 power-domain@RK3588_PD_RKVDEC0 {
977 #power-domain-cells = <0>;
979 power-domain@RK3588_PD_RKVDEC1 {
985 #power-domain-cells = <0>;
987 power-domain@RK3588_PD_RGA30 {
992 #power-domain-cells = <0>;
995 power-domain@RK3588_PD_VOP {
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1004 #power-domain-cells = <0>;
1006 power-domain@RK3588_PD_VO0 {
1016 #power-domain-cells = <0>;
1019 power-domain@RK3588_PD_VO1 {
1030 #power-domain-cells = <0>;
1032 power-domain@RK3588_PD_VI {
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1046 #power-domain-cells = <0>;
1048 power-domain@RK3588_PD_ISP1 {
1056 #power-domain-cells = <0>;
1058 power-domain@RK3588_PD_FEC {
1067 #power-domain-cells = <0>;
1070 power-domain@RK3588_PD_RGA31 {
1075 #power-domain-cells = <0>;
1077 power-domain@RK3588_PD_USB {
1091 #power-domain-cells = <0>;
1093 power-domain@RK3588_PD_GMAC {
1098 #power-domain-cells = <0>;
1100 power-domain@RK3588_PD_PCIE {
1105 #power-domain-cells = <0>;
1107 power-domain@RK3588_PD_SDIO {
1112 #power-domain-cells = <0>;
1114 power-domain@RK3588_PD_AUDIO {
1118 #power-domain-cells = <0>;
1120 power-domain@RK3588_PD_SDMMC {
1123 #power-domain-cells = <0>;
1128 vpu121: video-codec@fdb50000 {
1129 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
1132 interrupt-names = "vdpu";
1134 clock-names = "aclk", "hclk";
1136 power-domains = <&power RK3588_PD_VDPU>;
1140 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1143 clock-names = "aclk", "iface";
1145 power-domains = <&power RK3588_PD_VDPU>;
1146 #iommu-cells = <0>;
1150 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga";
1154 clock-names = "aclk", "hclk", "sclk";
1156 reset-names = "core", "axi", "ahb";
1157 power-domains = <&power RK3588_PD_VDPU>;
1160 vepu121_0: video-codec@fdba0000 {
1161 compatible = "rockchip,rk3588-vepu121";
1165 clock-names = "aclk", "hclk";
1167 power-domains = <&power RK3588_PD_VDPU>;
1171 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1175 clock-names = "aclk", "iface";
1176 power-domains = <&power RK3588_PD_VDPU>;
1177 #iommu-cells = <0>;
1180 vepu121_1: video-codec@fdba4000 {
1181 compatible = "rockchip,rk3588-vepu121";
1185 clock-names = "aclk", "hclk";
1187 power-domains = <&power RK3588_PD_VDPU>;
1191 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1195 clock-names = "aclk", "iface";
1196 power-domains = <&power RK3588_PD_VDPU>;
1197 #iommu-cells = <0>;
1200 vepu121_2: video-codec@fdba8000 {
1201 compatible = "rockchip,rk3588-vepu121";
1205 clock-names = "aclk", "hclk";
1207 power-domains = <&power RK3588_PD_VDPU>;
1211 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1215 clock-names = "aclk", "iface";
1216 power-domains = <&power RK3588_PD_VDPU>;
1217 #iommu-cells = <0>;
1220 vepu121_3: video-codec@fdbac000 {
1221 compatible = "rockchip,rk3588-vepu121";
1225 clock-names = "aclk", "hclk";
1227 power-domains = <&power RK3588_PD_VDPU>;
1231 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1235 clock-names = "aclk", "iface";
1236 power-domains = <&power RK3588_PD_VDPU>;
1237 #iommu-cells = <0>;
1240 av1d: video-codec@fdc70000 {
1241 compatible = "rockchip,rk3588-av1-vpu";
1244 interrupt-names = "vdpu";
1245 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
1246 assigned-clock-rates = <400000000>, <400000000>;
1248 clock-names = "aclk", "hclk";
1249 power-domains = <&power RK3588_PD_AV1>;
1254 compatible = "rockchip,rk3588-vop";
1256 reg-names = "vop", "gamma-lut";
1265 clock-names = "aclk",
1273 power-domains = <&power RK3588_PD_VOP>;
1275 rockchip,vop-grf = <&vop_grf>;
1276 rockchip,vo1-grf = <&vo1_grf>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1291 #address-cells = <1>;
1292 #size-cells = <0>;
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1311 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1315 clock-names = "aclk", "iface";
1316 #iommu-cells = <0>;
1317 power-domains = <&power RK3588_PD_VOP>;
1322 compatible = "rockchip,rk3588-i2s-tdm";
1326 clock-names = "mclk_tx", "mclk_rx", "hclk";
1327 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
1328 assigned-clock-parents = <&cru PLL_AUPLL>;
1330 dma-names = "tx";
1331 power-domains = <&power RK3588_PD_VO0>;
1333 reset-names = "tx-m";
1334 #sound-dai-cells = <0>;
1339 compatible = "rockchip,rk3588-i2s-tdm";
1343 clock-names = "mclk_tx", "mclk_rx", "hclk";
1344 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
1345 assigned-clock-parents = <&cru PLL_AUPLL>;
1347 dma-names = "tx";
1348 power-domains = <&power RK3588_PD_VO1>;
1350 reset-names = "tx-m";
1351 #sound-dai-cells = <0>;
1356 compatible = "rockchip,rk3588-i2s-tdm";
1360 clock-names = "mclk_tx", "mclk_rx", "hclk";
1361 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1362 assigned-clock-parents = <&cru PLL_AUPLL>;
1364 dma-names = "rx";
1365 power-domains = <&power RK3588_PD_VO1>;
1367 reset-names = "rx-m";
1368 #sound-dai-cells = <0>;
1373 compatible = "rockchip,rk3588-dw-hdmi-qp";
1381 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
1387 interrupt-names = "avp", "cec", "earc", "main", "hpd";
1389 pinctrl-names = "default";
1390 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
1392 power-domains = <&power RK3588_PD_VO1>;
1394 reset-names = "ref", "hdp";
1396 rockchip,vo-grf = <&vo1_grf>;
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1414 compatible = "rockchip,rk3588-qos", "syscon";
1419 compatible = "rockchip,rk3588-qos", "syscon";
1424 compatible = "rockchip,rk3588-qos", "syscon";
1429 compatible = "rockchip,rk3588-qos", "syscon";
1434 compatible = "rockchip,rk3588-qos", "syscon";
1439 compatible = "rockchip,rk3588-qos", "syscon";
1444 compatible = "rockchip,rk3588-qos", "syscon";
1449 compatible = "rockchip,rk3588-qos", "syscon";
1454 compatible = "rockchip,rk3588-qos", "syscon";
1459 compatible = "rockchip,rk3588-qos", "syscon";
1464 compatible = "rockchip,rk3588-qos", "syscon";
1469 compatible = "rockchip,rk3588-qos", "syscon";
1474 compatible = "rockchip,rk3588-qos", "syscon";
1479 compatible = "rockchip,rk3588-qos", "syscon";
1484 compatible = "rockchip,rk3588-qos", "syscon";
1489 compatible = "rockchip,rk3588-qos", "syscon";
1494 compatible = "rockchip,rk3588-qos", "syscon";
1499 compatible = "rockchip,rk3588-qos", "syscon";
1504 compatible = "rockchip,rk3588-qos", "syscon";
1509 compatible = "rockchip,rk3588-qos", "syscon";
1514 compatible = "rockchip,rk3588-qos", "syscon";
1519 compatible = "rockchip,rk3588-qos", "syscon";
1524 compatible = "rockchip,rk3588-qos", "syscon";
1529 compatible = "rockchip,rk3588-qos", "syscon";
1534 compatible = "rockchip,rk3588-qos", "syscon";
1539 compatible = "rockchip,rk3588-qos", "syscon";
1544 compatible = "rockchip,rk3588-qos", "syscon";
1549 compatible = "rockchip,rk3588-qos", "syscon";
1554 compatible = "rockchip,rk3588-qos", "syscon";
1559 compatible = "rockchip,rk3588-qos", "syscon";
1564 compatible = "rockchip,rk3588-qos", "syscon";
1569 compatible = "rockchip,rk3588-qos", "syscon";
1574 compatible = "rockchip,rk3588-qos", "syscon";
1579 compatible = "rockchip,rk3588-qos", "syscon";
1584 compatible = "rockchip,rk3588-qos", "syscon";
1589 compatible = "rockchip,rk3588-qos", "syscon";
1594 compatible = "rockchip,rk3588-qos", "syscon";
1599 compatible = "rockchip,rk3588-qos", "syscon";
1604 compatible = "rockchip,rk3588-qos", "syscon";
1609 compatible = "rockchip,rk3588-qos", "syscon";
1614 compatible = "rockchip,rk3588-qos", "syscon";
1619 compatible = "rockchip,rk3588-qos", "syscon";
1624 compatible = "rockchip,rk3588-qos", "syscon";
1629 compatible = "rockchip,rk3588-qos", "syscon";
1634 compatible = "rockchip,rk3588-qos", "syscon";
1639 compatible = "rockchip,rk3588-qos", "syscon";
1644 compatible = "rockchip,rk3588-qos", "syscon";
1649 compatible = "rockchip,rk3588-qos", "syscon";
1655 compatible = "rockchip,rk3588-dfi";
1664 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1665 bus-range = <0x30 0x3f>;
1669 clock-names = "aclk_mst", "aclk_slv",
1678 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1679 #interrupt-cells = <1>;
1680 interrupt-map-mask = <0 0 0 7>;
1681 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1685 linux,pci-domain = <3>;
1686 max-link-speed = <2>;
1687 msi-map = <0x3000 &its0 0x3000 0x1000>;
1688 iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>;
1689 num-lanes = <1>;
1691 phy-names = "pcie-phy";
1692 power-domains = <&power RK3588_PD_PCIE>;
1699 reg-names = "dbi", "apb", "config";
1701 reset-names = "pwr", "pipe";
1702 #address-cells = <3>;
1703 #size-cells = <2>;
1706 pcie2x1l1_intc: legacy-interrupt-controller {
1707 interrupt-controller;
1708 #address-cells = <0>;
1709 #interrupt-cells = <1>;
1710 interrupt-parent = <&gic>;
1716 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1717 bus-range = <0x40 0x4f>;
1721 clock-names = "aclk_mst", "aclk_slv",
1730 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1731 #interrupt-cells = <1>;
1732 interrupt-map-mask = <0 0 0 7>;
1733 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1737 linux,pci-domain = <4>;
1738 max-link-speed = <2>;
1739 msi-map = <0x4000 &its0 0x4000 0x1000>;
1740 iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>;
1741 num-lanes = <1>;
1743 phy-names = "pcie-phy";
1744 power-domains = <&power RK3588_PD_PCIE>;
1751 reg-names = "dbi", "apb", "config";
1753 reset-names = "pwr", "pipe";
1754 #address-cells = <3>;
1755 #size-cells = <2>;
1758 pcie2x1l2_intc: legacy-interrupt-controller {
1759 interrupt-controller;
1760 #address-cells = <0>;
1761 #interrupt-cells = <1>;
1762 interrupt-parent = <&gic>;
1768 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1772 interrupt-names = "macirq", "eth_wake_irq";
1776 clock-names = "stmmaceth", "clk_mac_ref",
1779 power-domains = <&power RK3588_PD_GMAC>;
1781 reset-names = "stmmaceth";
1783 rockchip,php-grf = <&php_grf>;
1784 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1785 snps,mixed-burst;
1786 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1787 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1792 compatible = "snps,dwmac-mdio";
1793 #address-cells = <0x1>;
1794 #size-cells = <0x0>;
1797 gmac1_stmmac_axi_setup: stmmac-axi-config {
1803 gmac1_mtl_rx_setup: rx-queues-config {
1804 snps,rx-queues-to-use = <2>;
1809 gmac1_mtl_tx_setup: tx-queues-config {
1810 snps,tx-queues-to-use = <2>;
1817 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1823 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1824 ports-implemented = <0x1>;
1825 #address-cells = <1>;
1826 #size-cells = <0>;
1829 sata-port@0 {
1831 hba-port-cap = <HBA_PORT_FBSCP>;
1833 phy-names = "sata-phy";
1834 snps,rx-ts-max = <32>;
1835 snps,tx-ts-max = <32>;
1840 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1846 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1847 ports-implemented = <0x1>;
1848 #address-cells = <1>;
1849 #size-cells = <0>;
1852 sata-port@0 {
1854 hba-port-cap = <HBA_PORT_FBSCP>;
1856 phy-names = "sata-phy";
1857 snps,rx-ts-max = <32>;
1858 snps,tx-ts-max = <32>;
1867 clock-names = "clk_sfc", "hclk_sfc";
1868 #address-cells = <1>;
1869 #size-cells = <0>;
1874 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1879 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1880 fifo-depth = <0x100>;
1881 max-frequency = <200000000>;
1882 pinctrl-names = "default";
1883 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1884 power-domains = <&power RK3588_PD_SDMMC>;
1889 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1894 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1895 fifo-depth = <0x100>;
1896 max-frequency = <200000000>;
1897 pinctrl-names = "default";
1898 pinctrl-0 = <&sdiom1_pins>;
1899 power-domains = <&power RK3588_PD_SDIO>;
1904 compatible = "rockchip,rk3588-dwcmshc";
1907 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1908 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1912 clock-names = "core", "bus", "axi", "block", "timer";
1913 max-frequency = <200000000>;
1914 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1916 pinctrl-names = "default";
1920 reset-names = "core", "bus", "axi", "block", "timer";
1925 compatible = "rockchip,rk3588-i2s-tdm";
1929 clock-names = "mclk_tx", "mclk_rx", "hclk";
1930 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1931 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1933 dma-names = "tx", "rx";
1934 power-domains = <&power RK3588_PD_AUDIO>;
1936 reset-names = "tx-m", "rx-m";
1937 rockchip,trcm-sync-tx-only;
1938 pinctrl-names = "default";
1939 pinctrl-0 = <&i2s0_lrck
1949 #sound-dai-cells = <0>;
1954 compatible = "rockchip,rk3588-i2s-tdm";
1958 clock-names = "mclk_tx", "mclk_rx", "hclk";
1960 dma-names = "tx", "rx";
1962 reset-names = "tx-m", "rx-m";
1963 rockchip,trcm-sync-tx-only;
1964 pinctrl-names = "default";
1965 pinctrl-0 = <&i2s1m0_lrck
1975 #sound-dai-cells = <0>;
1980 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1984 clock-names = "i2s_clk", "i2s_hclk";
1985 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1986 assigned-clock-parents = <&cru PLL_AUPLL>;
1988 dma-names = "tx", "rx";
1989 power-domains = <&power RK3588_PD_AUDIO>;
1990 pinctrl-names = "default";
1991 pinctrl-0 = <&i2s2m1_lrck
1995 #sound-dai-cells = <0>;
2000 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
2004 clock-names = "i2s_clk", "i2s_hclk";
2005 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
2006 assigned-clock-parents = <&cru PLL_AUPLL>;
2008 dma-names = "tx", "rx";
2009 power-domains = <&power RK3588_PD_AUDIO>;
2010 pinctrl-names = "default";
2011 pinctrl-0 = <&i2s3_lrck
2015 #sound-dai-cells = <0>;
2019 gic: interrupt-controller@fe600000 {
2020 compatible = "arm,gic-v3";
2024 interrupt-controller;
2025 mbi-alias = <0x0 0xfe610000>;
2026 mbi-ranges = <424 56>;
2027 msi-controller;
2029 #address-cells = <2>;
2030 #interrupt-cells = <4>;
2031 #size-cells = <2>;
2033 its0: msi-controller@fe640000 {
2034 compatible = "arm,gic-v3-its";
2036 msi-controller;
2037 #msi-cells = <1>;
2040 its1: msi-controller@fe660000 {
2041 compatible = "arm,gic-v3-its";
2043 msi-controller;
2044 #msi-cells = <1>;
2047 ppi-partitions {
2048 ppi_partition0: interrupt-partition-0 {
2052 ppi_partition1: interrupt-partition-1 {
2058 dmac0: dma-controller@fea10000 {
2063 arm,pl330-periph-burst;
2065 clock-names = "apb_pclk";
2066 #dma-cells = <1>;
2069 dmac1: dma-controller@fea30000 {
2074 arm,pl330-periph-burst;
2076 clock-names = "apb_pclk";
2077 #dma-cells = <1>;
2081 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2084 clock-names = "i2c", "pclk";
2086 pinctrl-0 = <&i2c1m0_xfer>;
2087 pinctrl-names = "default";
2088 #address-cells = <1>;
2089 #size-cells = <0>;
2094 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2097 clock-names = "i2c", "pclk";
2099 pinctrl-0 = <&i2c2m0_xfer>;
2100 pinctrl-names = "default";
2101 #address-cells = <1>;
2102 #size-cells = <0>;
2107 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2110 clock-names = "i2c", "pclk";
2112 pinctrl-0 = <&i2c3m0_xfer>;
2113 pinctrl-names = "default";
2114 #address-cells = <1>;
2115 #size-cells = <0>;
2120 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2123 clock-names = "i2c", "pclk";
2125 pinctrl-0 = <&i2c4m0_xfer>;
2126 pinctrl-names = "default";
2127 #address-cells = <1>;
2128 #size-cells = <0>;
2133 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2136 clock-names = "i2c", "pclk";
2138 pinctrl-0 = <&i2c5m0_xfer>;
2139 pinctrl-names = "default";
2140 #address-cells = <1>;
2141 #size-cells = <0>;
2146 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
2150 clock-names = "pclk", "timer";
2154 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
2157 clock-names = "tclk", "pclk";
2162 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2166 clock-names = "spiclk", "apb_pclk";
2168 dma-names = "tx", "rx";
2169 num-cs = <2>;
2170 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
2171 pinctrl-names = "default";
2172 #address-cells = <1>;
2173 #size-cells = <0>;
2178 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2182 clock-names = "spiclk", "apb_pclk";
2184 dma-names = "tx", "rx";
2185 num-cs = <2>;
2186 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
2187 pinctrl-names = "default";
2188 #address-cells = <1>;
2189 #size-cells = <0>;
2194 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2198 clock-names = "spiclk", "apb_pclk";
2200 dma-names = "tx", "rx";
2201 num-cs = <2>;
2202 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
2203 pinctrl-names = "default";
2204 #address-cells = <1>;
2205 #size-cells = <0>;
2210 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2214 clock-names = "spiclk", "apb_pclk";
2216 dma-names = "tx", "rx";
2217 num-cs = <2>;
2218 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
2219 pinctrl-names = "default";
2220 #address-cells = <1>;
2221 #size-cells = <0>;
2226 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2230 clock-names = "baudclk", "apb_pclk";
2232 dma-names = "tx", "rx";
2233 pinctrl-0 = <&uart1m1_xfer>;
2234 pinctrl-names = "default";
2235 reg-io-width = <4>;
2236 reg-shift = <2>;
2241 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2245 clock-names = "baudclk", "apb_pclk";
2247 dma-names = "tx", "rx";
2248 pinctrl-0 = <&uart2m1_xfer>;
2249 pinctrl-names = "default";
2250 reg-io-width = <4>;
2251 reg-shift = <2>;
2256 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2260 clock-names = "baudclk", "apb_pclk";
2262 dma-names = "tx", "rx";
2263 pinctrl-0 = <&uart3m1_xfer>;
2264 pinctrl-names = "default";
2265 reg-io-width = <4>;
2266 reg-shift = <2>;
2271 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2275 clock-names = "baudclk", "apb_pclk";
2277 dma-names = "tx", "rx";
2278 pinctrl-0 = <&uart4m1_xfer>;
2279 pinctrl-names = "default";
2280 reg-io-width = <4>;
2281 reg-shift = <2>;
2286 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2290 clock-names = "baudclk", "apb_pclk";
2292 dma-names = "tx", "rx";
2293 pinctrl-0 = <&uart5m1_xfer>;
2294 pinctrl-names = "default";
2295 reg-io-width = <4>;
2296 reg-shift = <2>;
2301 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2305 clock-names = "baudclk", "apb_pclk";
2307 dma-names = "tx", "rx";
2308 pinctrl-0 = <&uart6m1_xfer>;
2309 pinctrl-names = "default";
2310 reg-io-width = <4>;
2311 reg-shift = <2>;
2316 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2320 clock-names = "baudclk", "apb_pclk";
2322 dma-names = "tx", "rx";
2323 pinctrl-0 = <&uart7m1_xfer>;
2324 pinctrl-names = "default";
2325 reg-io-width = <4>;
2326 reg-shift = <2>;
2331 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2335 clock-names = "baudclk", "apb_pclk";
2337 dma-names = "tx", "rx";
2338 pinctrl-0 = <&uart8m1_xfer>;
2339 pinctrl-names = "default";
2340 reg-io-width = <4>;
2341 reg-shift = <2>;
2346 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2350 clock-names = "baudclk", "apb_pclk";
2352 dma-names = "tx", "rx";
2353 pinctrl-0 = <&uart9m1_xfer>;
2354 pinctrl-names = "default";
2355 reg-io-width = <4>;
2356 reg-shift = <2>;
2361 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2364 clock-names = "pwm", "pclk";
2365 pinctrl-0 = <&pwm4m0_pins>;
2366 pinctrl-names = "default";
2367 #pwm-cells = <3>;
2372 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2375 clock-names = "pwm", "pclk";
2376 pinctrl-0 = <&pwm5m0_pins>;
2377 pinctrl-names = "default";
2378 #pwm-cells = <3>;
2383 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2386 clock-names = "pwm", "pclk";
2387 pinctrl-0 = <&pwm6m0_pins>;
2388 pinctrl-names = "default";
2389 #pwm-cells = <3>;
2394 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2397 clock-names = "pwm", "pclk";
2398 pinctrl-0 = <&pwm7m0_pins>;
2399 pinctrl-names = "default";
2400 #pwm-cells = <3>;
2405 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2408 clock-names = "pwm", "pclk";
2409 pinctrl-0 = <&pwm8m0_pins>;
2410 pinctrl-names = "default";
2411 #pwm-cells = <3>;
2416 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2419 clock-names = "pwm", "pclk";
2420 pinctrl-0 = <&pwm9m0_pins>;
2421 pinctrl-names = "default";
2422 #pwm-cells = <3>;
2427 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2430 clock-names = "pwm", "pclk";
2431 pinctrl-0 = <&pwm10m0_pins>;
2432 pinctrl-names = "default";
2433 #pwm-cells = <3>;
2438 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2441 clock-names = "pwm", "pclk";
2442 pinctrl-0 = <&pwm11m0_pins>;
2443 pinctrl-names = "default";
2444 #pwm-cells = <3>;
2449 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2452 clock-names = "pwm", "pclk";
2453 pinctrl-0 = <&pwm12m0_pins>;
2454 pinctrl-names = "default";
2455 #pwm-cells = <3>;
2460 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2463 clock-names = "pwm", "pclk";
2464 pinctrl-0 = <&pwm13m0_pins>;
2465 pinctrl-names = "default";
2466 #pwm-cells = <3>;
2471 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2474 clock-names = "pwm", "pclk";
2475 pinctrl-0 = <&pwm14m0_pins>;
2476 pinctrl-names = "default";
2477 #pwm-cells = <3>;
2482 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2485 clock-names = "pwm", "pclk";
2486 pinctrl-0 = <&pwm15m0_pins>;
2487 pinctrl-names = "default";
2488 #pwm-cells = <3>;
2492 thermal_zones: thermal-zones {
2494 package_thermal: package-thermal {
2495 polling-delay-passive = <0>;
2496 polling-delay = <0>;
2497 thermal-sensors = <&tsadc 0>;
2500 package_crit: package-crit {
2509 bigcore0_thermal: bigcore0-thermal {
2510 polling-delay-passive = <100>;
2511 polling-delay = <0>;
2512 thermal-sensors = <&tsadc 1>;
2515 bigcore0_alert: bigcore0-alert {
2521 bigcore0_crit: bigcore0-crit {
2528 cooling-maps {
2531 cooling-device =
2539 bigcore2_thermal: bigcore2-thermal {
2540 polling-delay-passive = <100>;
2541 polling-delay = <0>;
2542 thermal-sensors = <&tsadc 2>;
2545 bigcore2_alert: bigcore2-alert {
2551 bigcore2_crit: bigcore2-crit {
2558 cooling-maps {
2561 cooling-device =
2569 little_core_thermal: littlecore-thermal {
2570 polling-delay-passive = <100>;
2571 polling-delay = <0>;
2572 thermal-sensors = <&tsadc 3>;
2575 littlecore_alert: littlecore-alert {
2581 littlecore_crit: littlecore-crit {
2588 cooling-maps {
2591 cooling-device =
2601 center_thermal: center-thermal {
2602 polling-delay-passive = <0>;
2603 polling-delay = <0>;
2604 thermal-sensors = <&tsadc 4>;
2607 center_crit: center-crit {
2615 gpu_thermal: gpu-thermal {
2616 polling-delay-passive = <100>;
2617 polling-delay = <0>;
2618 thermal-sensors = <&tsadc 5>;
2621 gpu_alert: gpu-alert {
2627 gpu_crit: gpu-crit {
2634 cooling-maps {
2637 cooling-device =
2643 npu_thermal: npu-thermal {
2644 polling-delay-passive = <0>;
2645 polling-delay = <0>;
2646 thermal-sensors = <&tsadc 6>;
2649 npu_crit: npu-crit {
2659 compatible = "rockchip,rk3588-tsadc";
2663 clock-names = "tsadc", "apb_pclk";
2664 assigned-clocks = <&cru CLK_TSADC>;
2665 assigned-clock-rates = <2000000>;
2667 reset-names = "tsadc-apb", "tsadc";
2668 rockchip,hw-tshut-temp = <120000>;
2669 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2670 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2671 pinctrl-0 = <&tsadc_shut_org>;
2672 pinctrl-1 = <&tsadc_gpio_func>;
2673 pinctrl-names = "default", "sleep";
2674 #thermal-sensor-cells = <1>;
2679 compatible = "rockchip,rk3588-saradc";
2682 #io-channel-cells = <1>;
2684 clock-names = "saradc", "apb_pclk";
2686 reset-names = "saradc-apb";
2691 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2694 clock-names = "i2c", "pclk";
2696 pinctrl-0 = <&i2c6m0_xfer>;
2697 pinctrl-names = "default";
2698 #address-cells = <1>;
2699 #size-cells = <0>;
2704 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2707 clock-names = "i2c", "pclk";
2709 pinctrl-0 = <&i2c7m0_xfer>;
2710 pinctrl-names = "default";
2711 #address-cells = <1>;
2712 #size-cells = <0>;
2717 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2720 clock-names = "i2c", "pclk";
2722 pinctrl-0 = <&i2c8m0_xfer>;
2723 pinctrl-names = "default";
2724 #address-cells = <1>;
2725 #size-cells = <0>;
2730 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2734 clock-names = "spiclk", "apb_pclk";
2736 dma-names = "tx", "rx";
2737 num-cs = <2>;
2738 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2739 pinctrl-names = "default";
2740 #address-cells = <1>;
2741 #size-cells = <0>;
2746 compatible = "rockchip,rk3588-otp";
2750 clock-names = "otp", "apb_pclk", "phy", "arb";
2753 reset-names = "otp", "apb", "arb";
2754 #address-cells = <1>;
2755 #size-cells = <1>;
2757 cpu_code: cpu-code@2 {
2765 cpub0_leakage: cpu-leakage@17 {
2769 cpub1_leakage: cpu-leakage@18 {
2773 cpul_leakage: cpu-leakage@19 {
2777 log_leakage: log-leakage@1a {
2781 gpu_leakage: gpu-leakage@1b {
2785 otp_cpu_version: cpu-version@1c {
2790 npu_leakage: npu-leakage@28 {
2794 codec_leakage: codec-leakage@29 {
2799 dmac2: dma-controller@fed10000 {
2804 arm,pl330-periph-burst;
2806 clock-names = "apb_pclk";
2807 #dma-cells = <1>;
2811 compatible = "rockchip,rk3588-hdptx-phy";
2814 clock-names = "ref", "apb";
2815 #phy-cells = <0>;
2820 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
2827 compatible = "rockchip,rk3588-usbdp-phy";
2829 #phy-cells = <1>;
2834 clock-names = "refclk", "immortal", "pclk", "utmi";
2840 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
2841 rockchip,u2phy-grf = <&usb2phy0_grf>;
2842 rockchip,usb-grf = <&usb_grf>;
2843 rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
2844 rockchip,vo-grf = <&vo0_grf>;
2849 compatible = "rockchip,rk3588-naneng-combphy";
2853 clock-names = "ref", "apb", "pipe";
2854 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2855 assigned-clock-rates = <100000000>;
2856 #phy-cells = <1>;
2858 reset-names = "phy", "apb";
2859 rockchip,pipe-grf = <&php_grf>;
2860 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2865 compatible = "rockchip,rk3588-naneng-combphy";
2869 clock-names = "ref", "apb", "pipe";
2870 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2871 assigned-clock-rates = <100000000>;
2872 #phy-cells = <1>;
2874 reset-names = "phy", "apb";
2875 rockchip,pipe-grf = <&php_grf>;
2876 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2881 compatible = "mmio-sram";
2884 #address-cells = <1>;
2885 #size-cells = <1>;
2889 compatible = "rockchip,rk3588-pinctrl";
2892 #address-cells = <2>;
2893 #size-cells = <2>;
2896 compatible = "rockchip,gpio-bank";
2900 gpio-controller;
2901 gpio-ranges = <&pinctrl 0 0 32>;
2902 interrupt-controller;
2903 #gpio-cells = <2>;
2904 #interrupt-cells = <2>;
2908 compatible = "rockchip,gpio-bank";
2912 gpio-controller;
2913 gpio-ranges = <&pinctrl 0 32 32>;
2914 interrupt-controller;
2915 #gpio-cells = <2>;
2916 #interrupt-cells = <2>;
2920 compatible = "rockchip,gpio-bank";
2924 gpio-controller;
2925 gpio-ranges = <&pinctrl 0 64 32>;
2926 interrupt-controller;
2927 #gpio-cells = <2>;
2928 #interrupt-cells = <2>;
2932 compatible = "rockchip,gpio-bank";
2936 gpio-controller;
2937 gpio-ranges = <&pinctrl 0 96 32>;
2938 interrupt-controller;
2939 #gpio-cells = <2>;
2940 #interrupt-cells = <2>;
2944 compatible = "rockchip,gpio-bank";
2948 gpio-controller;
2949 gpio-ranges = <&pinctrl 0 128 32>;
2950 interrupt-controller;
2951 #gpio-cells = <2>;
2952 #interrupt-cells = <2>;
2957 #include "rk3588-base-pinctrl.dtsi"