Lines Matching +full:rk3288 +full:- +full:vpu
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a55";
57 #cooling-cells = <2>;
58 enable-method = "psci";
59 i-cache-size = <0x8000>;
60 i-cache-line-size = <64>;
61 i-cache-sets = <128>;
62 d-cache-size = <0x8000>;
63 d-cache-line-size = <64>;
64 d-cache-sets = <128>;
65 next-level-cache = <&l3_cache>;
70 compatible = "arm,cortex-a55";
72 #cooling-cells = <2>;
73 enable-method = "psci";
74 i-cache-size = <0x8000>;
75 i-cache-line-size = <64>;
76 i-cache-sets = <128>;
77 d-cache-size = <0x8000>;
78 d-cache-line-size = <64>;
79 d-cache-sets = <128>;
80 next-level-cache = <&l3_cache>;
85 compatible = "arm,cortex-a55";
87 #cooling-cells = <2>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <128>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&l3_cache>;
100 compatible = "arm,cortex-a55";
102 #cooling-cells = <2>;
103 enable-method = "psci";
104 i-cache-size = <0x8000>;
105 i-cache-line-size = <64>;
106 i-cache-sets = <128>;
107 d-cache-size = <0x8000>;
108 d-cache-line-size = <64>;
109 d-cache-sets = <128>;
110 next-level-cache = <&l3_cache>;
115 * There are no private per-core L2 caches, but only the
118 l3_cache: l3-cache {
120 cache-level = <2>;
121 cache-unified;
122 cache-size = <0x80000>;
123 cache-line-size = <64>;
124 cache-sets = <512>;
127 display_subsystem: display-subsystem {
128 compatible = "rockchip,display-subsystem";
134 compatible = "arm,scmi-smc";
135 arm,smc-id = <0x82000010>;
137 #address-cells = <1>;
138 #size-cells = <0>;
142 #clock-cells = <1>;
147 hdmi_sound: hdmi-sound {
148 compatible = "simple-audio-card";
149 simple-audio-card,name = "HDMI";
150 simple-audio-card,format = "i2s";
151 simple-audio-card,mclk-fs = <256>;
154 simple-audio-card,codec {
155 sound-dai = <&hdmi>;
158 simple-audio-card,cpu {
159 sound-dai = <&i2s0_8ch>;
164 compatible = "arm,cortex-a55-pmu";
169 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
173 compatible = "arm,psci-1.0";
177 reserved-memory {
178 #address-cells = <2>;
179 #size-cells = <2>;
183 compatible = "arm,scmi-shmem";
185 no-map;
190 compatible = "arm,armv8-timer";
195 arm,no-tick-in-suspend;
199 compatible = "fixed-clock";
200 clock-frequency = <24000000>;
201 clock-output-names = "xin24m";
202 #clock-cells = <0>;
206 compatible = "fixed-clock";
207 clock-frequency = <32768>;
208 clock-output-names = "xin32k";
209 pinctrl-0 = <&clk32k_out0>;
210 pinctrl-names = "default";
211 #clock-cells = <0>;
215 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
219 clock-names = "sata", "pmalive", "rxoob";
222 phy-names = "sata-phy";
223 ports-implemented = <0x1>;
224 power-domains = <&power RK3568_PD_PIPE>;
229 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
233 clock-names = "sata", "pmalive", "rxoob";
236 phy-names = "sata-phy";
237 ports-implemented = <0x1>;
238 power-domains = <&power RK3568_PD_PIPE>;
243 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
248 clock-names = "ref_clk", "suspend_clk",
252 power-domains = <&power RK3568_PD_PIPE>;
259 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
264 clock-names = "ref_clk", "suspend_clk",
268 phy-names = "usb2-phy", "usb3-phy";
270 power-domains = <&power RK3568_PD_PIPE>;
276 gic: interrupt-controller@fd400000 {
277 compatible = "arm,gic-v3";
281 interrupt-controller;
282 #interrupt-cells = <3>;
283 mbi-alias = <0x0 0xfd410000>;
284 mbi-ranges = <296 24>;
285 msi-controller;
289 compatible = "generic-ehci";
295 phy-names = "usb";
300 compatible = "generic-ohci";
306 phy-names = "usb";
311 compatible = "generic-ehci";
317 phy-names = "usb";
322 compatible = "generic-ohci";
328 phy-names = "usb";
333 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
336 pmu_io_domains: io-domains {
337 compatible = "rockchip,rk3568-pmu-io-voltage-domain";
347 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
352 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
357 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
362 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
367 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
371 pmucru: clock-controller@fdd00000 {
372 compatible = "rockchip,rk3568-pmucru";
374 #clock-cells = <1>;
375 #reset-cells = <1>;
378 cru: clock-controller@fdd20000 {
379 compatible = "rockchip,rk3568-cru";
382 clock-names = "xin24m";
383 #clock-cells = <1>;
384 #reset-cells = <1>;
385 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
386 assigned-clock-rates = <32768>, <1200000000>, <200000000>;
387 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
392 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
396 clock-names = "i2c", "pclk";
397 pinctrl-0 = <&i2c0_xfer>;
398 pinctrl-names = "default";
399 #address-cells = <1>;
400 #size-cells = <0>;
405 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
409 clock-names = "baudclk", "apb_pclk";
411 pinctrl-0 = <&uart0_xfer>;
412 pinctrl-names = "default";
413 reg-io-width = <4>;
414 reg-shift = <2>;
419 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
422 clock-names = "pwm", "pclk";
423 pinctrl-0 = <&pwm0m0_pins>;
424 pinctrl-names = "default";
425 #pwm-cells = <3>;
430 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
433 clock-names = "pwm", "pclk";
434 pinctrl-0 = <&pwm1m0_pins>;
435 pinctrl-names = "default";
436 #pwm-cells = <3>;
441 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
444 clock-names = "pwm", "pclk";
445 pinctrl-0 = <&pwm2m0_pins>;
446 pinctrl-names = "default";
447 #pwm-cells = <3>;
452 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
455 clock-names = "pwm", "pclk";
456 pinctrl-0 = <&pwm3_pins>;
457 pinctrl-names = "default";
458 #pwm-cells = <3>;
462 pmu: power-management@fdd90000 {
463 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
466 power: power-controller {
467 compatible = "rockchip,rk3568-power-controller";
468 #power-domain-cells = <1>;
469 #address-cells = <1>;
470 #size-cells = <0>;
473 power-domain@RK3568_PD_GPU {
478 #power-domain-cells = <0>;
482 power-domain@RK3568_PD_VI {
489 #power-domain-cells = <0>;
492 power-domain@RK3568_PD_VO {
500 #power-domain-cells = <0>;
503 power-domain@RK3568_PD_RGA {
513 #power-domain-cells = <0>;
516 power-domain@RK3568_PD_VPU {
520 #power-domain-cells = <0>;
523 power-domain@RK3568_PD_RKVDEC {
527 #power-domain-cells = <0>;
530 power-domain@RK3568_PD_RKVENC {
536 #power-domain-cells = <0>;
542 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
547 interrupt-names = "job", "mmu", "gpu";
549 clock-names = "gpu", "bus";
550 #cooling-cells = <2>;
551 power-domains = <&power RK3568_PD_GPU>;
555 vpu: video-codec@fdea0400 { label
556 compatible = "rockchip,rk3568-vpu";
559 interrupt-names = "vdpu";
561 clock-names = "aclk", "hclk";
563 power-domains = <&power RK3568_PD_VPU>;
567 compatible = "rockchip,rk3568-iommu";
570 clock-names = "aclk", "iface";
572 power-domains = <&power RK3568_PD_VPU>;
573 #iommu-cells = <0>;
577 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
581 clock-names = "aclk", "hclk", "sclk";
583 reset-names = "core", "axi", "ahb";
584 power-domains = <&power RK3568_PD_RGA>;
587 vepu: video-codec@fdee0000 {
588 compatible = "rockchip,rk3568-vepu";
592 clock-names = "aclk", "hclk";
594 power-domains = <&power RK3568_PD_RGA>;
598 compatible = "rockchip,rk3568-iommu";
602 clock-names = "aclk", "iface";
603 power-domains = <&power RK3568_PD_RGA>;
604 #iommu-cells = <0>;
608 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
613 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
614 fifo-depth = <0x100>;
615 max-frequency = <150000000>;
617 reset-names = "reset";
622 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
626 interrupt-names = "macirq", "eth_wake_irq";
631 clock-names = "stmmaceth", "mac_clk_rx",
636 reset-names = "stmmaceth";
638 snps,axi-config = <&gmac1_stmmac_axi_setup>;
639 snps,mixed-burst;
640 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
641 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
646 compatible = "snps,dwmac-mdio";
647 #address-cells = <0x1>;
648 #size-cells = <0x0>;
651 gmac1_stmmac_axi_setup: stmmac-axi-config {
657 gmac1_mtl_rx_setup: rx-queues-config {
658 snps,rx-queues-to-use = <1>;
662 gmac1_mtl_tx_setup: tx-queues-config {
663 snps,tx-queues-to-use = <1>;
670 reg-names = "vop", "gamma-lut";
674 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
676 power-domains = <&power RK3568_PD_VO>;
681 #address-cells = <1>;
682 #size-cells = <0>;
686 #address-cells = <1>;
687 #size-cells = <0>;
692 #address-cells = <1>;
693 #size-cells = <0>;
698 #address-cells = <1>;
699 #size-cells = <0>;
705 compatible = "rockchip,rk3568-iommu";
709 clock-names = "aclk", "iface";
710 #iommu-cells = <0>;
711 power-domains = <&power RK3568_PD_VO>;
716 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
719 clock-names = "pclk";
721 phy-names = "dphy";
723 power-domains = <&power RK3568_PD_VO>;
724 reset-names = "apb";
730 #address-cells = <1>;
731 #size-cells = <0>;
744 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
747 clock-names = "pclk";
749 phy-names = "dphy";
751 power-domains = <&power RK3568_PD_VO>;
752 reset-names = "apb";
758 #address-cells = <1>;
759 #size-cells = <0>;
772 compatible = "rockchip,rk3568-dw-hdmi";
780 clock-names = "iahb", "isfr", "cec", "ref";
781 pinctrl-names = "default";
782 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
783 power-domains = <&power RK3568_PD_VO>;
784 reg-io-width = <4>;
786 #sound-dai-cells = <0>;
790 #address-cells = <1>;
791 #size-cells = <0>;
804 compatible = "rockchip,rk3568-qos", "syscon";
809 compatible = "rockchip,rk3568-qos", "syscon";
814 compatible = "rockchip,rk3568-qos", "syscon";
819 compatible = "rockchip,rk3568-qos", "syscon";
824 compatible = "rockchip,rk3568-qos", "syscon";
829 compatible = "rockchip,rk3568-qos", "syscon";
834 compatible = "rockchip,rk3568-qos", "syscon";
839 compatible = "rockchip,rk3568-qos", "syscon";
844 compatible = "rockchip,rk3568-qos", "syscon";
849 compatible = "rockchip,rk3568-qos", "syscon";
854 compatible = "rockchip,rk3568-qos", "syscon";
859 compatible = "rockchip,rk3568-qos", "syscon";
864 compatible = "rockchip,rk3568-qos", "syscon";
869 compatible = "rockchip,rk3568-qos", "syscon";
874 compatible = "rockchip,rk3568-qos", "syscon";
879 compatible = "rockchip,rk3568-qos", "syscon";
884 compatible = "rockchip,rk3568-qos", "syscon";
889 compatible = "rockchip,rk3568-qos", "syscon";
894 compatible = "rockchip,rk3568-qos", "syscon";
899 compatible = "rockchip,rk3568-qos", "syscon";
904 compatible = "rockchip,rk3568-qos", "syscon";
909 compatible = "rockchip,rk3568-qos", "syscon";
914 compatible = "rockchip,rk3568-qos", "syscon";
919 compatible = "rockchip,rk3568-qos", "syscon";
924 compatible = "rockchip,rk3568-dfi";
931 compatible = "rockchip,rk3568-pcie";
935 reg-names = "dbi", "apb", "config";
941 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
942 bus-range = <0x0 0xf>;
946 clock-names = "aclk_mst", "aclk_slv",
949 #interrupt-cells = <1>;
950 interrupt-map-mask = <0 0 0 7>;
951 interrupt-map = <0 0 0 1 &pcie_intc 0>,
955 linux,pci-domain = <0>;
956 num-ib-windows = <6>;
957 num-ob-windows = <2>;
958 max-link-speed = <2>;
959 msi-map = <0x0 &gic 0x0 0x1000>;
960 num-lanes = <1>;
962 phy-names = "pcie-phy";
963 power-domains = <&power RK3568_PD_PIPE>;
968 reset-names = "pipe";
969 #address-cells = <3>;
970 #size-cells = <2>;
973 pcie_intc: legacy-interrupt-controller {
974 #address-cells = <0>;
975 #interrupt-cells = <1>;
976 interrupt-controller;
977 interrupt-parent = <&gic>;
983 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
988 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
989 fifo-depth = <0x100>;
990 max-frequency = <150000000>;
992 reset-names = "reset";
997 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1002 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1003 fifo-depth = <0x100>;
1004 max-frequency = <150000000>;
1006 reset-names = "reset";
1015 clock-names = "clk_sfc", "hclk_sfc";
1016 pinctrl-0 = <&fspi_pins>;
1017 pinctrl-names = "default";
1022 compatible = "rockchip,rk3568-dwcmshc";
1025 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1026 assigned-clock-rates = <200000000>, <24000000>;
1030 clock-names = "core", "bus", "axi", "block", "timer";
1035 compatible = "rockchip,rk3568-rng";
1038 clock-names = "core", "ahb";
1044 compatible = "rockchip,rk3568-i2s-tdm";
1047 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1048 assigned-clock-rates = <1188000000>, <1188000000>;
1050 clock-names = "mclk_tx", "mclk_rx", "hclk";
1052 dma-names = "tx";
1054 reset-names = "tx-m", "rx-m";
1056 #sound-dai-cells = <0>;
1061 compatible = "rockchip,rk3568-i2s-tdm";
1064 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1065 assigned-clock-rates = <1188000000>, <1188000000>;
1068 clock-names = "mclk_tx", "mclk_rx", "hclk";
1070 dma-names = "rx", "tx";
1072 reset-names = "tx-m", "rx-m";
1074 pinctrl-names = "default";
1075 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1081 #sound-dai-cells = <0>;
1086 compatible = "rockchip,rk3568-i2s-tdm";
1089 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1090 assigned-clock-rates = <1188000000>;
1092 clock-names = "mclk_tx", "mclk_rx", "hclk";
1094 dma-names = "tx", "rx";
1096 reset-names = "tx-m";
1098 pinctrl-names = "default";
1099 pinctrl-0 = <&i2s2m0_sclktx
1103 #sound-dai-cells = <0>;
1108 compatible = "rockchip,rk3568-i2s-tdm";
1113 clock-names = "mclk_tx", "mclk_rx", "hclk";
1115 dma-names = "tx", "rx";
1117 reset-names = "tx-m", "rx-m";
1119 #sound-dai-cells = <0>;
1124 compatible = "rockchip,rk3568-pdm";
1128 clock-names = "pdm_clk", "pdm_hclk";
1130 dma-names = "rx";
1131 pinctrl-0 = <&pdmm0_clk
1137 pinctrl-names = "default";
1139 reset-names = "pdm-m";
1140 #sound-dai-cells = <0>;
1145 compatible = "rockchip,rk3568-spdif";
1148 clock-names = "mclk", "hclk";
1151 dma-names = "tx";
1152 pinctrl-names = "default";
1153 pinctrl-0 = <&spdifm0_tx>;
1154 #sound-dai-cells = <0>;
1158 dmac0: dma-controller@fe530000 {
1163 arm,pl330-periph-burst;
1165 clock-names = "apb_pclk";
1166 #dma-cells = <1>;
1169 dmac1: dma-controller@fe550000 {
1174 arm,pl330-periph-burst;
1176 clock-names = "apb_pclk";
1177 #dma-cells = <1>;
1181 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1185 clock-names = "i2c", "pclk";
1186 pinctrl-0 = <&i2c1_xfer>;
1187 pinctrl-names = "default";
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1194 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1198 clock-names = "i2c", "pclk";
1199 pinctrl-0 = <&i2c2m0_xfer>;
1200 pinctrl-names = "default";
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1207 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1211 clock-names = "i2c", "pclk";
1212 pinctrl-0 = <&i2c3m0_xfer>;
1213 pinctrl-names = "default";
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1220 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1224 clock-names = "i2c", "pclk";
1225 pinctrl-0 = <&i2c4m0_xfer>;
1226 pinctrl-names = "default";
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1233 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1237 clock-names = "i2c", "pclk";
1238 pinctrl-0 = <&i2c5m0_xfer>;
1239 pinctrl-names = "default";
1240 #address-cells = <1>;
1241 #size-cells = <0>;
1246 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1250 clock-names = "tclk", "pclk";
1254 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1258 clock-names = "spiclk", "apb_pclk";
1260 dma-names = "tx", "rx";
1261 pinctrl-names = "default";
1262 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1269 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1273 clock-names = "spiclk", "apb_pclk";
1275 dma-names = "tx", "rx";
1276 pinctrl-names = "default";
1277 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1278 #address-cells = <1>;
1279 #size-cells = <0>;
1284 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1288 clock-names = "spiclk", "apb_pclk";
1290 dma-names = "tx", "rx";
1291 pinctrl-names = "default";
1292 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1299 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1303 clock-names = "spiclk", "apb_pclk";
1305 dma-names = "tx", "rx";
1306 pinctrl-names = "default";
1307 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1314 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1318 clock-names = "baudclk", "apb_pclk";
1320 pinctrl-0 = <&uart1m0_xfer>;
1321 pinctrl-names = "default";
1322 reg-io-width = <4>;
1323 reg-shift = <2>;
1328 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1332 clock-names = "baudclk", "apb_pclk";
1334 pinctrl-0 = <&uart2m0_xfer>;
1335 pinctrl-names = "default";
1336 reg-io-width = <4>;
1337 reg-shift = <2>;
1342 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1346 clock-names = "baudclk", "apb_pclk";
1348 pinctrl-0 = <&uart3m0_xfer>;
1349 pinctrl-names = "default";
1350 reg-io-width = <4>;
1351 reg-shift = <2>;
1356 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1360 clock-names = "baudclk", "apb_pclk";
1362 pinctrl-0 = <&uart4m0_xfer>;
1363 pinctrl-names = "default";
1364 reg-io-width = <4>;
1365 reg-shift = <2>;
1370 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1374 clock-names = "baudclk", "apb_pclk";
1376 pinctrl-0 = <&uart5m0_xfer>;
1377 pinctrl-names = "default";
1378 reg-io-width = <4>;
1379 reg-shift = <2>;
1384 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1388 clock-names = "baudclk", "apb_pclk";
1390 pinctrl-0 = <&uart6m0_xfer>;
1391 pinctrl-names = "default";
1392 reg-io-width = <4>;
1393 reg-shift = <2>;
1398 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1402 clock-names = "baudclk", "apb_pclk";
1404 pinctrl-0 = <&uart7m0_xfer>;
1405 pinctrl-names = "default";
1406 reg-io-width = <4>;
1407 reg-shift = <2>;
1412 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1416 clock-names = "baudclk", "apb_pclk";
1418 pinctrl-0 = <&uart8m0_xfer>;
1419 pinctrl-names = "default";
1420 reg-io-width = <4>;
1421 reg-shift = <2>;
1426 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1430 clock-names = "baudclk", "apb_pclk";
1432 pinctrl-0 = <&uart9m0_xfer>;
1433 pinctrl-names = "default";
1434 reg-io-width = <4>;
1435 reg-shift = <2>;
1439 thermal_zones: thermal-zones {
1440 cpu_thermal: cpu-thermal {
1441 polling-delay-passive = <100>;
1442 polling-delay = <1000>;
1444 thermal-sensors = <&tsadc 0>;
1464 cooling-maps {
1467 cooling-device =
1476 gpu_thermal: gpu-thermal {
1477 polling-delay-passive = <20>; /* milliseconds */
1478 polling-delay = <1000>; /* milliseconds */
1480 thermal-sensors = <&tsadc 1>;
1483 gpu_threshold: gpu-threshold {
1488 gpu_target: gpu-target {
1493 gpu_crit: gpu-crit {
1500 cooling-maps {
1503 cooling-device =
1511 compatible = "rockchip,rk3568-tsadc";
1514 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1515 assigned-clock-rates = <17000000>, <700000>;
1517 clock-names = "tsadc", "apb_pclk";
1521 rockchip,hw-tshut-temp = <95000>;
1522 pinctrl-names = "default", "sleep";
1523 pinctrl-0 = <&tsadc_shutorg>;
1524 pinctrl-1 = <&tsadc_pin>;
1525 #thermal-sensor-cells = <1>;
1530 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1534 clock-names = "saradc", "apb_pclk";
1536 reset-names = "saradc-apb";
1537 #io-channel-cells = <1>;
1542 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1545 clock-names = "pwm", "pclk";
1546 pinctrl-0 = <&pwm4_pins>;
1547 pinctrl-names = "default";
1548 #pwm-cells = <3>;
1553 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1556 clock-names = "pwm", "pclk";
1557 pinctrl-0 = <&pwm5_pins>;
1558 pinctrl-names = "default";
1559 #pwm-cells = <3>;
1564 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1567 clock-names = "pwm", "pclk";
1568 pinctrl-0 = <&pwm6_pins>;
1569 pinctrl-names = "default";
1570 #pwm-cells = <3>;
1575 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1578 clock-names = "pwm", "pclk";
1579 pinctrl-0 = <&pwm7_pins>;
1580 pinctrl-names = "default";
1581 #pwm-cells = <3>;
1586 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1589 clock-names = "pwm", "pclk";
1590 pinctrl-0 = <&pwm8m0_pins>;
1591 pinctrl-names = "default";
1592 #pwm-cells = <3>;
1597 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1600 clock-names = "pwm", "pclk";
1601 pinctrl-0 = <&pwm9m0_pins>;
1602 pinctrl-names = "default";
1603 #pwm-cells = <3>;
1608 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1611 clock-names = "pwm", "pclk";
1612 pinctrl-0 = <&pwm10m0_pins>;
1613 pinctrl-names = "default";
1614 #pwm-cells = <3>;
1619 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1622 clock-names = "pwm", "pclk";
1623 pinctrl-0 = <&pwm11m0_pins>;
1624 pinctrl-names = "default";
1625 #pwm-cells = <3>;
1630 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1633 clock-names = "pwm", "pclk";
1634 pinctrl-0 = <&pwm12m0_pins>;
1635 pinctrl-names = "default";
1636 #pwm-cells = <3>;
1641 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1644 clock-names = "pwm", "pclk";
1645 pinctrl-0 = <&pwm13m0_pins>;
1646 pinctrl-names = "default";
1647 #pwm-cells = <3>;
1652 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1655 clock-names = "pwm", "pclk";
1656 pinctrl-0 = <&pwm14m0_pins>;
1657 pinctrl-names = "default";
1658 #pwm-cells = <3>;
1663 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1666 clock-names = "pwm", "pclk";
1667 pinctrl-0 = <&pwm15m0_pins>;
1668 pinctrl-names = "default";
1669 #pwm-cells = <3>;
1674 compatible = "rockchip,rk3568-naneng-combphy";
1679 clock-names = "ref", "apb", "pipe";
1680 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1681 assigned-clock-rates = <100000000>;
1683 reset-names = "phy";
1684 rockchip,pipe-grf = <&pipegrf>;
1685 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1686 #phy-cells = <1>;
1691 compatible = "rockchip,rk3568-naneng-combphy";
1696 clock-names = "ref", "apb", "pipe";
1697 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1698 assigned-clock-rates = <100000000>;
1700 reset-names = "phy";
1701 rockchip,pipe-grf = <&pipegrf>;
1702 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1703 #phy-cells = <1>;
1708 compatible = "rockchip,rk3568-csi-dphy";
1711 clock-names = "pclk";
1712 #phy-cells = <0>;
1714 reset-names = "apb";
1719 dsi_dphy0: mipi-dphy@fe850000 {
1720 compatible = "rockchip,rk3568-dsi-dphy";
1722 clock-names = "ref", "pclk";
1724 #phy-cells = <0>;
1725 power-domains = <&power RK3568_PD_VO>;
1726 reset-names = "apb";
1731 dsi_dphy1: mipi-dphy@fe860000 {
1732 compatible = "rockchip,rk3568-dsi-dphy";
1734 clock-names = "ref", "pclk";
1736 #phy-cells = <0>;
1737 power-domains = <&power RK3568_PD_VO>;
1738 reset-names = "apb";
1744 compatible = "rockchip,rk3568-usb2phy";
1747 clock-names = "phyclk";
1748 clock-output-names = "clk_usbphy0_480m";
1751 #clock-cells = <0>;
1754 usb2phy0_host: host-port {
1755 #phy-cells = <0>;
1759 usb2phy0_otg: otg-port {
1760 #phy-cells = <0>;
1766 compatible = "rockchip,rk3568-usb2phy";
1769 clock-names = "phyclk";
1770 clock-output-names = "clk_usbphy1_480m";
1773 #clock-cells = <0>;
1776 usb2phy1_host: host-port {
1777 #phy-cells = <0>;
1781 usb2phy1_otg: otg-port {
1782 #phy-cells = <0>;
1788 compatible = "rockchip,rk3568-pinctrl";
1791 #address-cells = <2>;
1792 #size-cells = <2>;
1796 compatible = "rockchip,gpio-bank";
1800 gpio-controller;
1801 gpio-ranges = <&pinctrl 0 0 32>;
1802 #gpio-cells = <2>;
1803 interrupt-controller;
1804 #interrupt-cells = <2>;
1808 compatible = "rockchip,gpio-bank";
1812 gpio-controller;
1813 gpio-ranges = <&pinctrl 0 32 32>;
1814 #gpio-cells = <2>;
1815 interrupt-controller;
1816 #interrupt-cells = <2>;
1820 compatible = "rockchip,gpio-bank";
1824 gpio-controller;
1825 gpio-ranges = <&pinctrl 0 64 32>;
1826 #gpio-cells = <2>;
1827 interrupt-controller;
1828 #interrupt-cells = <2>;
1832 compatible = "rockchip,gpio-bank";
1836 gpio-controller;
1837 gpio-ranges = <&pinctrl 0 96 32>;
1838 #gpio-cells = <2>;
1839 interrupt-controller;
1840 #interrupt-cells = <2>;
1844 compatible = "rockchip,gpio-bank";
1848 gpio-controller;
1849 gpio-ranges = <&pinctrl 0 128 32>;
1850 #gpio-cells = <2>;
1851 interrupt-controller;
1852 #interrupt-cells = <2>;
1857 #include "rk3568-pinctrl.dtsi"