Lines Matching +full:io +full:- +full:width
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
29 #address-cells = <1>;
30 #size-cells = <0>;
32 cpu-map {
50 compatible = "arm,cortex-a53";
53 enable-method = "psci";
57 compatible = "arm,cortex-a53";
60 enable-method = "psci";
64 compatible = "arm,cortex-a53";
67 enable-method = "psci";
71 compatible = "arm,cortex-a53";
74 enable-method = "psci";
79 compatible = "arm,psci-1.0", "arm,psci-0.2";
84 compatible = "arm,armv8-timer";
91 xin24m: clock-xin24m {
92 compatible = "fixed-clock";
93 clock-frequency = <24000000>;
94 clock-output-names = "xin24m";
95 #clock-cells = <0>;
99 compatible = "simple-bus";
101 #address-cells = <2>;
102 #size-cells = <2>;
104 gic: interrupt-controller@fed01000 {
105 compatible = "arm,gic-400";
112 interrupt-controller;
113 #address-cells = <0>;
114 #interrupt-cells = <3>;
118 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
120 clock-frequency = <24000000>;
122 reg-io-width = <4>;
123 reg-shift = <2>;
128 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
131 reg-io-width = <4>;
132 reg-shift = <2>;
137 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
140 reg-io-width = <4>;
141 reg-shift = <2>;
146 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
148 reg-io-width = <4>;
149 reg-shift = <2>;
154 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
157 reg-io-width = <4>;
158 reg-shift = <2>;
163 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
166 reg-io-width = <4>;
167 reg-shift = <2>;
172 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
175 reg-io-width = <4>;
176 reg-shift = <2>;
181 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
184 reg-io-width = <4>;
185 reg-shift = <2>;