Lines Matching full:cpg
9 #include <dt-bindings/clock/r9a08g045-cpg.h>
42 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
83 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
85 power-domains = <&cpg>;
86 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
101 clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
103 power-domains = <&cpg>;
104 resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>;
119 clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
121 power-domains = <&cpg>;
122 resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>;
137 clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>;
139 power-domains = <&cpg>;
140 resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>;
155 clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>;
157 power-domains = <&cpg>;
158 resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>;
173 clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>;
175 power-domains = <&cpg>;
176 resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>;
187 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>;
189 power-domains = <&cpg>;
190 resets = <&cpg R9A08G045_VBAT_BRESETN>;
198 clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>,
199 <&cpg CPG_MOD R9A08G045_ADC_PCLK>;
201 resets = <&cpg R9A08G045_ADC_PRESETN>,
202 <&cpg R9A08G045_ADC_ADRST_N>;
204 power-domains = <&cpg>;
251 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
254 power-domains = <&cpg>;
255 resets = <&cpg R9A08G045_VBAT_BRESETN>;
272 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>;
274 resets = <&cpg R9A08G045_I2C0_MRST>;
275 power-domains = <&cpg>;
294 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>;
296 resets = <&cpg R9A08G045_I2C1_MRST>;
297 power-domains = <&cpg>;
316 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>;
318 resets = <&cpg R9A08G045_I2C2_MRST>;
319 power-domains = <&cpg>;
338 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>;
340 resets = <&cpg R9A08G045_I2C3_MRST>;
341 power-domains = <&cpg>;
355 clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>,
356 <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>,
359 resets = <&cpg R9A08G045_SSI0_RST_M2_REG>;
362 power-domains = <&cpg>;
375 clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>,
376 <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>,
379 resets = <&cpg R9A08G045_SSI1_RST_M2_REG>;
382 power-domains = <&cpg>;
395 clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>,
396 <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>,
399 resets = <&cpg R9A08G045_SSI2_RST_M2_REG>;
402 power-domains = <&cpg>;
415 clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
416 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
419 resets = <&cpg R9A08G045_SSI3_RST_M2_REG>;
422 power-domains = <&cpg>;
427 cpg: clock-controller@11010000 { label
428 compatible = "renesas,r9a08g045-cpg";
458 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
459 power-domains = <&cpg>;
460 resets = <&cpg R9A08G045_GPIO_RSTN>,
461 <&cpg R9A08G045_GPIO_PORT_RESETN>,
462 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
529 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
530 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
532 power-domains = <&cpg>;
533 resets = <&cpg R9A08G045_IA55_RESETN>;
563 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
564 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
566 power-domains = <&cpg>;
567 resets = <&cpg R9A08G045_DMAC_ARESETN>,
568 <&cpg R9A08G045_DMAC_RST_ASYNC>;
579 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
580 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
581 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
582 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
584 resets = <&cpg R9A08G045_SDHI0_IXRST>;
585 power-domains = <&cpg>;
594 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
595 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
596 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
597 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
599 resets = <&cpg R9A08G045_SDHI1_IXRST>;
600 power-domains = <&cpg>;
609 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
610 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
611 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
612 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
614 resets = <&cpg R9A08G045_SDHI2_IXRST>;
615 power-domains = <&cpg>;
627 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
628 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
629 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
631 resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
632 power-domains = <&cpg>;
646 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
647 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
648 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
650 resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
651 power-domains = <&cpg>;
670 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
671 <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
676 resets = <&cpg R9A08G045_WDT0_PRESETN>;
677 power-domains = <&cpg>;