Lines Matching full:cpg_mod
83 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
101 clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
119 clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
137 clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>;
155 clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>;
173 clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>;
187 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>;
198 clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>,
199 <&cpg CPG_MOD R9A08G045_ADC_PCLK>;
251 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
272 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>;
294 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>;
316 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>;
338 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>;
355 clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>,
356 <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>,
375 clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>,
376 <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>,
395 clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>,
396 <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>,
415 clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
416 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
458 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
529 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
530 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
563 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
564 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
579 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
580 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
581 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
582 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
594 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
595 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
596 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
597 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
609 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
610 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
611 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
612 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
627 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
628 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
629 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
646 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
647 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
648 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
670 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
671 <&cpg CPG_MOD R9A08G045_WDT0_CLK>;