Lines Matching full:mmcc
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
691 clocks = <&mmcc AHB_CLK_SRC>;
1521 mmcc: clock-controller@c8c0000 { label
1522 compatible = "qcom,mmcc-sdm630";
1555 power-domains = <&mmcc MDSS_GDSC>;
1557 clocks = <&mmcc MDSS_AHB_CLK>,
1558 <&mmcc MDSS_AXI_CLK>,
1559 <&mmcc MDSS_VSYNC_CLK>,
1560 <&mmcc MDSS_MDP_CLK>;
1584 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1585 <&mmcc MDSS_VSYNC_CLK>;
1588 clocks = <&mmcc MDSS_AHB_CLK>,
1589 <&mmcc MDSS_AXI_CLK>,
1590 <&mmcc MDSS_MDP_CLK>,
1591 <&mmcc MDSS_VSYNC_CLK>;
1662 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1663 <&mmcc PCLK0_CLK_SRC>;
1667 clocks = <&mmcc MDSS_MDP_CLK>,
1668 <&mmcc MDSS_BYTE0_CLK>,
1669 <&mmcc MDSS_BYTE0_INTF_CLK>,
1670 <&mmcc MNOC_AHB_CLK>,
1671 <&mmcc MDSS_AHB_CLK>,
1672 <&mmcc MDSS_AXI_CLK>,
1673 <&mmcc MISC_AHB_CLK>,
1674 <&mmcc MDSS_PCLK0_CLK>,
1675 <&mmcc MDSS_ESC0_CLK>;
1721 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2022 clocks = <&mmcc CAMSS_AHB_CLK>,
2023 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2024 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2025 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2026 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2027 <&mmcc CAMSS_CSI0_AHB_CLK>,
2028 <&mmcc CAMSS_CSI0_CLK>,
2029 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2030 <&mmcc CAMSS_CSI0PIX_CLK>,
2031 <&mmcc CAMSS_CSI0RDI_CLK>,
2032 <&mmcc CAMSS_CSI1_AHB_CLK>,
2033 <&mmcc CAMSS_CSI1_CLK>,
2034 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2035 <&mmcc CAMSS_CSI1PIX_CLK>,
2036 <&mmcc CAMSS_CSI1RDI_CLK>,
2037 <&mmcc CAMSS_CSI2_AHB_CLK>,
2038 <&mmcc CAMSS_CSI2_CLK>,
2039 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2040 <&mmcc CAMSS_CSI2PIX_CLK>,
2041 <&mmcc CAMSS_CSI2RDI_CLK>,
2042 <&mmcc CAMSS_CSI3_AHB_CLK>,
2043 <&mmcc CAMSS_CSI3_CLK>,
2044 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2045 <&mmcc CAMSS_CSI3PIX_CLK>,
2046 <&mmcc CAMSS_CSI3RDI_CLK>,
2047 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2048 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2049 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2050 <&mmcc CSIPHY_AHB2CRIF_CLK>,
2051 <&mmcc CAMSS_CSI_VFE0_CLK>,
2052 <&mmcc CAMSS_CSI_VFE1_CLK>,
2053 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2054 <&mmcc THROTTLE_CAMSS_AXI_CLK>,
2055 <&mmcc CAMSS_TOP_AHB_CLK>,
2056 <&mmcc CAMSS_VFE0_AHB_CLK>,
2057 <&mmcc CAMSS_VFE0_CLK>,
2058 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2059 <&mmcc CAMSS_VFE1_AHB_CLK>,
2060 <&mmcc CAMSS_VFE1_CLK>,
2061 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2062 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
2063 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
2112 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2113 <&mmcc CAMSS_VFE1_GDSC>;
2129 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2130 <&mmcc CAMSS_CCI_CLK>;
2132 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2133 <&mmcc CAMSS_CCI_AHB_CLK>,
2134 <&mmcc CAMSS_CCI_CLK>,
2135 <&mmcc CAMSS_AHB_CLK>;
2143 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2164 clocks = <&mmcc VIDEO_CORE_CLK>,
2165 <&mmcc VIDEO_AHB_CLK>,
2166 <&mmcc VIDEO_AXI_CLK>,
2167 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
2194 power-domains = <&mmcc VENUS_GDSC>;
2199 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2201 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2206 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2208 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2216 clocks = <&mmcc MNOC_AHB_CLK>,
2217 <&mmcc BIMC_SMMU_AHB_CLK>,
2218 <&mmcc BIMC_SMMU_AXI_CLK>;