Lines Matching +full:remote +full:- +full:endpoint
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
9 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11 #include <dt-bindings/clock/qcom,sa8775p-videocc.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 interrupt-parent = <&intc>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 xo_board_clk: xo-board-clk {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <38400000>;
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32000>;
41 #address-cells = <2>;
42 #size-cells = <0>;
46 compatible = "arm,cortex-a78c";
48 enable-method = "psci";
49 next-level-cache = <&l2_0>;
50 power-domains = <&cpu_pd0>;
51 power-domain-names = "psci";
52 capacity-dmips-mhz = <1946>;
53 dynamic-power-coefficient = <472>;
55 l2_0: l2-cache {
57 cache-level = <2>;
58 cache-unified;
59 next-level-cache = <&l3_0>;
65 compatible = "arm,cortex-a78c";
67 enable-method = "psci";
68 next-level-cache = <&l2_1>;
69 power-domains = <&cpu_pd1>;
70 power-domain-names = "psci";
71 capacity-dmips-mhz = <1946>;
72 dynamic-power-coefficient = <472>;
74 l2_1: l2-cache {
76 cache-level = <2>;
77 cache-unified;
78 next-level-cache = <&l3_0>;
84 compatible = "arm,cortex-a78c";
86 enable-method = "psci";
87 next-level-cache = <&l2_2>;
88 power-domains = <&cpu_pd2>;
89 power-domain-names = "psci";
90 capacity-dmips-mhz = <1946>;
91 dynamic-power-coefficient = <507>;
93 l2_2: l2-cache {
95 cache-level = <2>;
96 cache-unified;
97 next-level-cache = <&l3_0>;
103 compatible = "arm,cortex-a78c";
105 enable-method = "psci";
106 next-level-cache = <&l2_3>;
107 power-domains = <&cpu_pd3>;
108 power-domain-names = "psci";
109 capacity-dmips-mhz = <1946>;
110 dynamic-power-coefficient = <507>;
112 l2_3: l2-cache {
114 cache-level = <2>;
115 cache-unified;
116 next-level-cache = <&l3_0>;
122 compatible = "arm,cortex-a55";
124 enable-method = "psci";
125 next-level-cache = <&l2_4>;
126 power-domains = <&cpu_pd4>;
127 power-domain-names = "psci";
128 capacity-dmips-mhz = <1024>;
129 dynamic-power-coefficient = <100>;
131 l2_4: l2-cache {
133 cache-level = <2>;
134 cache-unified;
135 next-level-cache = <&l3_1>;
141 compatible = "arm,cortex-a55";
143 enable-method = "psci";
144 next-level-cache = <&l2_5>;
145 power-domains = <&cpu_pd5>;
146 power-domain-names = "psci";
147 capacity-dmips-mhz = <1024>;
148 dynamic-power-coefficient = <100>;
150 l2_5: l2-cache {
152 cache-level = <2>;
153 cache-unified;
154 next-level-cache = <&l3_1>;
160 compatible = "arm,cortex-a55";
162 enable-method = "psci";
163 next-level-cache = <&l2_6>;
164 power-domains = <&cpu_pd6>;
165 power-domain-names = "psci";
166 capacity-dmips-mhz = <1024>;
167 dynamic-power-coefficient = <100>;
169 l2_6: l2-cache {
171 cache-level = <2>;
172 cache-unified;
173 next-level-cache = <&l3_1>;
179 compatible = "arm,cortex-a55";
181 enable-method = "psci";
182 next-level-cache = <&l2_7>;
183 power-domains = <&cpu_pd7>;
184 power-domain-names = "psci";
185 capacity-dmips-mhz = <1024>;
186 dynamic-power-coefficient = <100>;
188 l2_7: l2-cache {
190 cache-level = <2>;
191 cache-unified;
192 next-level-cache = <&l3_1>;
196 cpu-map {
234 l3_0: l3-cache-0 {
236 cache-level = <3>;
237 cache-unified;
240 l3_1: l3-cache-1 {
242 cache-level = <3>;
243 cache-unified;
246 idle-states {
247 entry-method = "psci";
249 little_cpu_sleep_0: cpu-sleep-0-0 {
250 compatible = "arm,idle-state";
251 idle-state-name = "silver-power-collapse";
252 arm,psci-suspend-param = <0x40000003>;
253 entry-latency-us = <449>;
254 exit-latency-us = <801>;
255 min-residency-us = <1574>;
256 local-timer-stop;
259 little_cpu_sleep_1: cpu-sleep-0-1 {
260 compatible = "arm,idle-state";
261 idle-state-name = "silver-rail-power-collapse";
262 arm,psci-suspend-param = <0x40000004>;
263 entry-latency-us = <602>;
264 exit-latency-us = <961>;
265 min-residency-us = <4288>;
266 local-timer-stop;
269 big_cpu_sleep_0: cpu-sleep-1-0 {
270 compatible = "arm,idle-state";
271 idle-state-name = "gold-power-collapse";
272 arm,psci-suspend-param = <0x40000003>;
273 entry-latency-us = <549>;
274 exit-latency-us = <901>;
275 min-residency-us = <1774>;
276 local-timer-stop;
279 big_cpu_sleep_1: cpu-sleep-1-1 {
280 compatible = "arm,idle-state";
281 idle-state-name = "gold-rail-power-collapse";
282 arm,psci-suspend-param = <0x40000004>;
283 entry-latency-us = <702>;
284 exit-latency-us = <1061>;
285 min-residency-us = <4488>;
286 local-timer-stop;
290 domain-idle-states {
291 silver_cluster_sleep: cluster-sleep-0 {
292 compatible = "domain-idle-state";
293 arm,psci-suspend-param = <0x41000044>;
294 entry-latency-us = <2552>;
295 exit-latency-us = <2848>;
296 min-residency-us = <5908>;
299 gold_cluster_sleep: cluster-sleep-1 {
300 compatible = "domain-idle-state";
301 arm,psci-suspend-param = <0x41000044>;
302 entry-latency-us = <2752>;
303 exit-latency-us = <3048>;
304 min-residency-us = <6118>;
307 system_sleep: domain-sleep {
308 compatible = "domain-idle-state";
309 arm,psci-suspend-param = <0x42000144>;
310 entry-latency-us = <3263>;
311 exit-latency-us = <6562>;
312 min-residency-us = <9987>;
317 dummy_eud: dummy-sink {
318 compatible = "arm,coresight-dummy-sink";
320 in-ports {
322 eud_in: endpoint {
323 remote-endpoint = <&swao_rep_out1>;
331 compatible = "qcom,scm-qcs8300", "qcom,scm";
332 qcom,dload-mode = <&tcsr 0x13000>;
342 clk_virt: interconnect-0 {
343 compatible = "qcom,qcs8300-clk-virt";
344 #interconnect-cells = <2>;
345 qcom,bcm-voters = <&apps_bcm_voter>;
348 mc_virt: interconnect-1 {
349 compatible = "qcom,qcs8300-mc-virt";
350 #interconnect-cells = <2>;
351 qcom,bcm-voters = <&apps_bcm_voter>;
354 pmu-a55 {
355 compatible = "arm,cortex-a55-pmu";
359 pmu-a78 {
360 compatible = "arm,cortex-a78-pmu";
365 compatible = "arm,psci-1.0";
368 cpu_pd0: power-domain-cpu0 {
369 #power-domain-cells = <0>;
370 power-domains = <&cluster_pd0>;
371 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
374 cpu_pd1: power-domain-cpu1 {
375 #power-domain-cells = <0>;
376 power-domains = <&cluster_pd0>;
377 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
380 cpu_pd2: power-domain-cpu2 {
381 #power-domain-cells = <0>;
382 power-domains = <&cluster_pd0>;
383 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
386 cpu_pd3: power-domain-cpu3 {
387 #power-domain-cells = <0>;
388 power-domains = <&cluster_pd0>;
389 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
392 cpu_pd4: power-domain-cpu4 {
393 #power-domain-cells = <0>;
394 power-domains = <&cluster_pd1>;
395 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
398 cpu_pd5: power-domain-cpu5 {
399 #power-domain-cells = <0>;
400 power-domains = <&cluster_pd1>;
401 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
404 cpu_pd6: power-domain-cpu6 {
405 #power-domain-cells = <0>;
406 power-domains = <&cluster_pd1>;
407 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
410 cpu_pd7: power-domain-cpu7 {
411 #power-domain-cells = <0>;
412 power-domains = <&cluster_pd1>;
413 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
416 cluster_pd0: power-domain-cluster0 {
417 #power-domain-cells = <0>;
418 power-domains = <&system_pd>;
419 domain-idle-states = <&gold_cluster_sleep>;
422 cluster_pd1: power-domain-cluster1 {
423 #power-domain-cells = <0>;
424 power-domains = <&system_pd>;
425 domain-idle-states = <&silver_cluster_sleep>;
428 system_pd: power-domain-system {
429 #power-domain-cells = <0>;
430 domain-idle-states = <&system_sleep>;
434 reserved-memory {
435 #address-cells = <2>;
436 #size-cells = <2>;
439 aop_image_mem: aop-image-region@90800000 {
441 no-map;
444 aop_cmd_db_mem: aop-cmd-db-region@90860000 {
445 compatible = "qcom,cmd-db";
447 no-map;
453 no-map;
457 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {
459 no-map;
462 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 {
464 no-map;
467 camera_mem: camera-region@95200000 {
469 no-map;
472 adsp_mem: adsp-region@95c00000 {
473 no-map;
477 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 {
479 no-map;
482 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 {
484 no-map;
487 gpdsp_mem: gpdsp-region@97b00000 {
489 no-map;
492 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 {
494 no-map;
497 cdsp_mem: cdsp-region@99980000 {
499 no-map;
502 gpu_microcode_mem: gpu-microcode-region@9b780000 {
504 no-map;
507 cvp_mem: cvp-region@9b782000 {
509 no-map;
512 video_mem: video-region@9be82000 {
514 no-map;
518 smp2p-adsp {
520 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
527 qcom,local-pid = <0>;
528 qcom,remote-pid = <2>;
530 smp2p_adsp_in: slave-kernel {
531 qcom,entry-name = "slave-kernel";
532 interrupt-controller;
533 #interrupt-cells = <2>;
536 smp2p_adsp_out: master-kernel {
537 qcom,entry-name = "master-kernel";
538 #qcom,smem-state-cells = <1>;
542 smp2p-cdsp {
544 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
551 qcom,local-pid = <0>;
552 qcom,remote-pid = <5>;
554 smp2p_cdsp_in: slave-kernel {
555 qcom,entry-name = "slave-kernel";
556 interrupt-controller;
557 #interrupt-cells = <2>;
560 smp2p_cdsp_out: master-kernel {
561 qcom,entry-name = "master-kernel";
562 #qcom,smem-state-cells = <1>;
566 smp2p-gpdsp {
568 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
575 qcom,local-pid = <0>;
576 qcom,remote-pid = <17>;
578 smp2p_gpdsp_in: slave-kernel {
579 qcom,entry-name = "slave-kernel";
580 interrupt-controller;
581 #interrupt-cells = <2>;
584 smp2p_gpdsp_out: master-kernel {
585 qcom,entry-name = "master-kernel";
586 #qcom,smem-state-cells = <1>;
591 compatible = "simple-bus";
593 #address-cells = <2>;
594 #size-cells = <2>;
596 gcc: clock-controller@100000 {
597 compatible = "qcom,qcs8300-gcc";
599 #clock-cells = <1>;
600 #reset-cells = <1>;
601 #power-domain-cells = <1>;
615 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
618 interrupt-controller;
619 #interrupt-cells = <3>;
620 #mbox-cells = <2>;
624 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom";
626 #address-cells = <1>;
627 #size-cells = <1>;
631 compatible = "qcom,geni-se-qup";
636 clock-names = "m-ahb",
637 "s-ahb";
638 #address-cells = <2>;
639 #size-cells = <2>;
643 compatible = "qcom,geni-debug-uart";
646 clock-names = "se";
647 pinctrl-0 = <&qup_uart7_default>;
648 pinctrl-names = "default";
654 interconnect-names = "qup-core",
655 "qup-config";
661 compatible = "qcom,qcs8300-trng", "qcom,trng";
666 compatible = "qcom,qcs8300-config-noc";
668 #interconnect-cells = <2>;
669 qcom,bcm-voters = <&apps_bcm_voter>;
673 compatible = "qcom,qcs8300-system-noc";
675 #interconnect-cells = <2>;
676 qcom,bcm-voters = <&apps_bcm_voter>;
680 compatible = "qcom,qcs8300-aggre1-noc";
682 #interconnect-cells = <2>;
683 qcom,bcm-voters = <&apps_bcm_voter>;
687 compatible = "qcom,qcs8300-aggre2-noc";
689 #interconnect-cells = <2>;
690 qcom,bcm-voters = <&apps_bcm_voter>;
694 compatible = "qcom,qcs8300-pcie-anoc";
696 #interconnect-cells = <2>;
697 qcom,bcm-voters = <&apps_bcm_voter>;
701 compatible = "qcom,qcs8300-gpdsp-anoc";
703 #interconnect-cells = <2>;
704 qcom,bcm-voters = <&apps_bcm_voter>;
708 compatible = "qcom,qcs8300-mmss-noc";
710 #interconnect-cells = <2>;
711 qcom,bcm-voters = <&apps_bcm_voter>;
715 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
719 phy-names = "ufsphy";
720 lanes-per-direction = <2>;
721 #reset-cells = <1>;
723 reset-names = "rst";
725 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
726 required-opps = <&rpmhpd_opp_nom>;
729 dma-coherent;
735 interconnect-names = "ufs-ddr",
736 "cpu-ufs";
746 clock-names = "core_clk",
754 freq-table-hz = <75000000 300000000>,
767 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy";
776 clock-names = "ref",
779 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
782 reset-names = "ufsphy";
784 #phy-cells = <0>;
788 cryptobam: dma-controller@1dc4000 {
789 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
792 #dma-cells = <1>;
794 qcom,controlled-remotely;
795 num-channels = <20>;
796 qcom,num-ees = <4>;
802 compatible = "qcom,qcs8300-qce", "qcom,qce";
805 dma-names = "rx", "tx";
810 interconnect-names = "memory";
814 compatible = "qcom,qcs8300-inline-crypto-engine",
815 "qcom,inline-crypto-engine";
821 compatible = "qcom,tcsr-mutex";
823 #hwlock-cells = <1>;
827 compatible = "qcom,qcs8300-tcsr", "syscon";
832 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas";
835 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
840 interrupt-names = "wdog",
844 "stop-ack";
847 clock-names = "xo";
849 power-domains = <&rpmhpd RPMHPD_LCX>,
851 power-domain-names = "lcx",
854 memory-region = <&adsp_mem>;
858 qcom,smem-states = <&smp2p_adsp_out 0>;
859 qcom,smem-state-names = "stop";
863 remoteproc_adsp_glink: glink-edge {
864 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
871 qcom,remote-pid = <2>;
875 qcom,glink-channels = "fastrpcglink-apps-dsp";
877 memory-region = <&adsp_rpc_remote_heap_mem>;
880 #address-cells = <1>;
881 #size-cells = <0>;
883 compute-cb@3 {
884 compatible = "qcom,fastrpc-compute-cb";
887 dma-coherent;
890 compute-cb@4 {
891 compatible = "qcom,fastrpc-compute-cb";
894 dma-coherent;
897 compute-cb@5 {
898 compatible = "qcom,fastrpc-compute-cb";
901 dma-coherent;
908 compatible = "qcom,qcs8300-lpass-ag-noc";
910 #interconnect-cells = <2>;
911 qcom,bcm-voters = <&apps_bcm_voter>;
915 compatible = "arm,coresight-stm", "arm,primecell";
918 reg-names = "stm-base",
919 "stm-stimulus-base";
922 clock-names = "apb_pclk";
924 out-ports {
926 stm_out: endpoint {
927 remote-endpoint = <&funnel0_in7>;
934 compatible = "qcom,coresight-tpda", "arm,primecell";
938 clock-names = "apb_pclk";
940 in-ports {
941 #address-cells = <1>;
942 #size-cells = <0>;
947 qdss_tpda_in1: endpoint {
948 remote-endpoint = <&qdss_tpdm1_out>;
953 out-ports {
955 qdss_tpda_out: endpoint {
956 remote-endpoint = <&funnel0_in6>;
963 compatible = "qcom,coresight-tpdm", "arm,primecell";
967 clock-names = "apb_pclk";
969 qcom,cmb-element-bits = <32>;
970 qcom,cmb-msrs-num = <32>;
972 out-ports {
974 qdss_tpdm1_out: endpoint {
975 remote-endpoint = <&qdss_tpda_in1>;
982 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
986 clock-names = "apb_pclk";
988 in-ports {
989 #address-cells = <1>;
990 #size-cells = <0>;
995 funnel0_in6: endpoint {
996 remote-endpoint = <&qdss_tpda_out>;
1003 funnel0_in7: endpoint {
1004 remote-endpoint = <&stm_out>;
1009 out-ports {
1011 funnel0_out: endpoint {
1012 remote-endpoint = <&qdss_funnel_in0>;
1019 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1023 clock-names = "apb_pclk";
1025 in-ports {
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1032 funnel1_in4: endpoint {
1033 remote-endpoint = <&apss_funnel1_out>;
1040 funnel1_in5: endpoint {
1041 remote-endpoint = <&dlct0_funnel_out>;
1048 funnel1_in6: endpoint {
1049 remote-endpoint = <&dlmm_funnel_out>;
1056 funnel1_in7: endpoint {
1057 remote-endpoint = <&dlst_ch_funnel_out>;
1062 out-ports {
1064 funnel1_out: endpoint {
1065 remote-endpoint = <&qdss_funnel_in1>;
1072 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1076 clock-names = "apb_pclk";
1078 in-ports {
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1085 qdss_funnel_in0: endpoint {
1086 remote-endpoint = <&funnel0_out>;
1093 qdss_funnel_in1: endpoint {
1094 remote-endpoint = <&funnel1_out>;
1099 out-ports {
1101 qdss_funnel_out: endpoint {
1102 remote-endpoint = <&aoss_funnel_in7>;
1109 compatible = "qcom,coresight-tpdm", "arm,primecell";
1113 clock-names = "apb_pclk";
1115 qcom,cmb-element-bits = <32>;
1116 qcom,cmb-msrs-num = <32>;
1118 out-ports {
1120 prng_tpdm_out: endpoint {
1121 remote-endpoint = <&dlct0_tpda_in19>;
1128 compatible = "qcom,coresight-tpdm", "arm,primecell";
1132 clock-names = "apb_pclk";
1134 qcom,cmb-element-bits = <64>;
1135 qcom,cmb-msrs-num = <32>;
1136 qcom,dsb-element-bits = <32>;
1137 qcom,dsb-msrs-num = <32>;
1139 out-ports {
1141 pimem_tpdm_out: endpoint {
1142 remote-endpoint = <&dlct0_tpda_in25>;
1149 compatible = "qcom,coresight-tpdm", "arm,primecell";
1153 clock-names = "apb_pclk";
1155 qcom,dsb-element-bits = <32>;
1156 qcom,dsb-msrs-num = <32>;
1158 out-ports {
1160 dlst_ch_tpdm0_out: endpoint {
1161 remote-endpoint = <&dlst_ch_tpda_in8>;
1168 compatible = "qcom,coresight-tpda", "arm,primecell";
1172 clock-names = "apb_pclk";
1174 in-ports {
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1181 dlst_ch_tpda_in8: endpoint {
1182 remote-endpoint = <&dlst_ch_tpdm0_out>;
1187 out-ports {
1189 dlst_ch_tpda_out: endpoint {
1190 remote-endpoint = <&dlst_ch_funnel_in0>;
1197 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1201 clock-names = "apb_pclk";
1203 in-ports {
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1210 dlst_ch_funnel_in0: endpoint {
1211 remote-endpoint = <&dlst_ch_tpda_out>;
1218 dlst_ch_funnel_in4: endpoint {
1219 remote-endpoint = <&dlst_funnel_out>;
1226 dlst_ch_funnel_in6: endpoint {
1227 remote-endpoint = <&gdsp_funnel_out>;
1232 out-ports {
1234 dlst_ch_funnel_out: endpoint {
1235 remote-endpoint = <&funnel1_in7>;
1242 compatible = "qcom,coresight-tpdm", "arm,primecell";
1246 clock-names = "apb_pclk";
1248 qcom,dsb-element-bits = <32>;
1249 qcom,dsb-msrs-num = <32>;
1251 out-ports {
1253 turing2_tpdm_out: endpoint {
1254 remote-endpoint = <&turing2_funnel_in0>;
1261 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1265 clock-names = "apb_pclk";
1267 in-ports {
1269 turing2_funnel_in0: endpoint {
1270 remote-endpoint = <&turing2_tpdm_out>;
1275 out-ports {
1277 turing2_funnel_out0: endpoint {
1278 remote-endpoint = <&gdsp_tpda_in5>;
1285 compatible = "qcom,coresight-tpdm", "arm,primecell";
1289 clock-names = "apb_pclk";
1291 qcom,dsb-element-bits = <32>;
1292 qcom,dsb-msrs-num = <32>;
1294 out-ports {
1296 dlmm_tpdm0_out: endpoint {
1297 remote-endpoint = <&dlmm_tpda_in27>;
1304 compatible = "qcom,coresight-tpda", "arm,primecell";
1308 clock-names = "apb_pclk";
1310 in-ports {
1311 #address-cells = <1>;
1312 #size-cells = <0>;
1317 dlmm_tpda_in27: endpoint {
1318 remote-endpoint = <&dlmm_tpdm0_out>;
1323 out-ports {
1325 dlmm_tpda_out: endpoint {
1326 remote-endpoint = <&dlmm_funnel_in0>;
1333 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1337 clock-names = "apb_pclk";
1339 in-ports {
1341 dlmm_funnel_in0: endpoint {
1342 remote-endpoint = <&dlmm_tpda_out>;
1347 out-ports {
1349 dlmm_funnel_out: endpoint {
1350 remote-endpoint = <&funnel1_in6>;
1357 compatible = "qcom,coresight-tpdm", "arm,primecell";
1361 clock-names = "apb_pclk";
1363 qcom,dsb-element-bits = <32>;
1364 qcom,dsb-msrs-num = <32>;
1366 out-ports {
1368 dlct0_tpdm0_out: endpoint {
1369 remote-endpoint = <&dlct0_tpda_in26>;
1376 compatible = "qcom,coresight-tpda", "arm,primecell";
1380 clock-names = "apb_pclk";
1382 in-ports {
1383 #address-cells = <1>;
1384 #size-cells = <0>;
1389 dlct0_tpda_in19: endpoint {
1390 remote-endpoint = <&prng_tpdm_out>;
1397 dlct0_tpda_in25: endpoint {
1398 remote-endpoint = <&pimem_tpdm_out>;
1405 dlct0_tpda_in26: endpoint {
1406 remote-endpoint = <&dlct0_tpdm0_out>;
1411 out-ports {
1413 dlct0_tpda_out: endpoint {
1414 remote-endpoint = <&dlct0_funnel_in0>;
1421 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1425 clock-names = "apb_pclk";
1427 in-ports {
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1434 dlct0_funnel_in0: endpoint {
1435 remote-endpoint = <&dlct0_tpda_out>;
1442 dlct0_funnel_in4: endpoint {
1443 remote-endpoint = <&ddr_funnel5_out>;
1448 out-ports {
1450 dlct0_funnel_out: endpoint {
1451 remote-endpoint = <&funnel1_in5>;
1458 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1462 clock-names = "apb_pclk";
1464 in-ports {
1465 #address-cells = <1>;
1466 #size-cells = <0>;
1471 aoss_funnel_in6: endpoint {
1472 remote-endpoint = <&aoss_tpda_out>;
1479 aoss_funnel_in7: endpoint {
1480 remote-endpoint = <&qdss_funnel_out>;
1485 out-ports {
1487 aoss_funnel_out: endpoint {
1488 remote-endpoint = <&etf0_in>;
1495 compatible = "arm,coresight-tmc", "arm,primecell";
1499 clock-names = "apb_pclk";
1501 in-ports {
1503 etf0_in: endpoint {
1504 remote-endpoint = <&aoss_funnel_out>;
1509 out-ports {
1511 etf0_out: endpoint {
1512 remote-endpoint = <&swao_rep_in>;
1519 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1523 clock-names = "apb_pclk";
1525 in-ports {
1527 swao_rep_in: endpoint {
1528 remote-endpoint = <&etf0_out>;
1533 out-ports {
1534 #address-cells = <1>;
1535 #size-cells = <0>;
1540 swao_rep_out1: endpoint {
1541 remote-endpoint = <&eud_in>;
1548 compatible = "qcom,coresight-tpda", "arm,primecell";
1552 clock-names = "apb_pclk";
1554 in-ports {
1555 #address-cells = <1>;
1556 #size-cells = <0>;
1561 aoss_tpda_in0: endpoint {
1562 remote-endpoint = <&aoss_tpdm0_out>;
1569 aoss_tpda_in1: endpoint {
1570 remote-endpoint = <&aoss_tpdm1_out>;
1577 aoss_tpda_in2: endpoint {
1578 remote-endpoint = <&aoss_tpdm2_out>;
1585 aoss_tpda_in3: endpoint {
1586 remote-endpoint = <&aoss_tpdm3_out>;
1593 aoss_tpda_in4: endpoint {
1594 remote-endpoint = <&aoss_tpdm4_out>;
1599 out-ports {
1601 aoss_tpda_out: endpoint {
1602 remote-endpoint = <&aoss_funnel_in6>;
1609 compatible = "qcom,coresight-tpdm", "arm,primecell";
1613 clock-names = "apb_pclk";
1615 qcom,cmb-element-bits = <64>;
1616 qcom,cmb-msrs-num = <32>;
1618 out-ports {
1620 aoss_tpdm0_out: endpoint {
1621 remote-endpoint = <&aoss_tpda_in0>;
1628 compatible = "qcom,coresight-tpdm", "arm,primecell";
1632 clock-names = "apb_pclk";
1634 qcom,cmb-element-bits = <64>;
1635 qcom,cmb-msrs-num = <32>;
1637 out-ports {
1639 aoss_tpdm1_out: endpoint {
1640 remote-endpoint = <&aoss_tpda_in1>;
1647 compatible = "qcom,coresight-tpdm", "arm,primecell";
1651 clock-names = "apb_pclk";
1653 qcom,cmb-element-bits = <64>;
1654 qcom,cmb-msrs-num = <32>;
1656 out-ports {
1658 aoss_tpdm2_out: endpoint {
1659 remote-endpoint = <&aoss_tpda_in2>;
1666 compatible = "qcom,coresight-tpdm", "arm,primecell";
1670 clock-names = "apb_pclk";
1672 qcom,cmb-element-bits = <64>;
1673 qcom,cmb-msrs-num = <32>;
1675 out-ports {
1677 aoss_tpdm3_out: endpoint {
1678 remote-endpoint = <&aoss_tpda_in3>;
1685 compatible = "qcom,coresight-tpdm", "arm,primecell";
1689 clock-names = "apb_pclk";
1691 qcom,dsb-element-bits = <32>;
1692 qcom,dsb-msrs-num = <32>;
1694 out-ports {
1696 aoss_tpdm4_out: endpoint {
1697 remote-endpoint = <&aoss_tpda_in4>;
1704 compatible = "arm,coresight-cti", "arm,primecell";
1708 clock-names = "apb_pclk";
1712 compatible = "qcom,coresight-tpdm", "arm,primecell";
1716 clock-names = "apb_pclk";
1718 qcom,dsb-element-bits = <32>;
1719 qcom,dsb-msrs-num = <32>;
1721 out-ports {
1723 turing0_tpdm0_out: endpoint {
1724 remote-endpoint = <&turing0_tpda_in0>;
1731 compatible = "qcom,coresight-tpda", "arm,primecell";
1735 clock-names = "apb_pclk";
1737 in-ports {
1739 turing0_tpda_in0: endpoint {
1740 remote-endpoint = <&turing0_tpdm0_out>;
1745 out-ports {
1747 turing0_tpda_out: endpoint {
1748 remote-endpoint = <&turing0_funnel_in0>;
1755 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1759 clock-names = "apb_pclk";
1761 in-ports {
1763 turing0_funnel_in0: endpoint {
1764 remote-endpoint = <&turing0_tpda_out>;
1769 out-ports {
1771 turing0_funnel_out: endpoint {
1772 remote-endpoint = <&gdsp_funnel_in4>;
1779 compatible = "arm,coresight-cti", "arm,primecell";
1783 clock-names = "apb_pclk";
1787 compatible = "qcom,coresight-tpdm", "arm,primecell";
1791 clock-names = "apb_pclk";
1793 qcom,dsb-element-bits = <32>;
1794 qcom,dsb-msrs-num = <32>;
1796 out-ports {
1798 gdsp_tpdm0_out: endpoint {
1799 remote-endpoint = <&gdsp_tpda_in8>;
1806 compatible = "qcom,coresight-tpda", "arm,primecell";
1810 clock-names = "apb_pclk";
1812 in-ports {
1813 #address-cells = <1>;
1814 #size-cells = <0>;
1819 gdsp_tpda_in5: endpoint {
1820 remote-endpoint = <&turing2_funnel_out0>;
1827 gdsp_tpda_in8: endpoint {
1828 remote-endpoint = <&gdsp_tpdm0_out>;
1833 out-ports {
1835 gdsp_tpda_out: endpoint {
1836 remote-endpoint = <&gdsp_funnel_in0>;
1843 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1847 clock-names = "apb_pclk";
1849 in-ports {
1850 #address-cells = <1>;
1851 #size-cells = <0>;
1856 gdsp_funnel_in0: endpoint {
1857 remote-endpoint = <&gdsp_tpda_out>;
1864 gdsp_funnel_in4: endpoint {
1865 remote-endpoint = <&turing0_funnel_out>;
1870 out-ports {
1872 gdsp_funnel_out: endpoint {
1873 remote-endpoint = <&dlst_ch_funnel_in6>;
1880 compatible = "qcom,coresight-tpdm", "arm,primecell";
1884 clock-names = "apb_pclk";
1886 qcom,dsb-element-bits = <32>;
1887 qcom,dsb-msrs-num = <32>;
1889 out-ports {
1891 dlst_tpdm0_out: endpoint {
1892 remote-endpoint = <&dlst_tpda_in8>;
1899 compatible = "qcom,coresight-tpda", "arm,primecell";
1903 clock-names = "apb_pclk";
1905 in-ports {
1906 #address-cells = <1>;
1907 #size-cells = <0>;
1912 dlst_tpda_in8: endpoint {
1913 remote-endpoint = <&dlst_tpdm0_out>;
1918 out-ports {
1920 dlst_tpda_out: endpoint {
1921 remote-endpoint = <&dlst_funnel_in0>;
1928 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1932 clock-names = "apb_pclk";
1934 in-ports {
1936 dlst_funnel_in0: endpoint {
1937 remote-endpoint = <&dlst_tpda_out>;
1942 out-ports {
1944 dlst_funnel_out: endpoint {
1945 remote-endpoint = <&dlst_ch_funnel_in4>;
1952 compatible = "qcom,coresight-tpdm", "arm,primecell";
1956 clock-names = "apb_pclk";
1958 qcom,dsb-element-bits = <32>;
1959 qcom,dsb-msrs-num = <32>;
1960 qcom,cmb-element-bits = <32>;
1961 qcom,cmb-msrs-num = <32>;
1963 out-ports {
1965 ddr_tpdm3_out: endpoint {
1966 remote-endpoint = <&ddr_tpda_in4>;
1973 compatible = "qcom,coresight-tpda", "arm,primecell";
1977 clock-names = "apb_pclk";
1979 in-ports {
1980 #address-cells = <1>;
1981 #size-cells = <0>;
1986 ddr_tpda_in0: endpoint {
1987 remote-endpoint = <&ddr_funnel0_out0>;
1994 ddr_tpda_in1: endpoint {
1995 remote-endpoint = <&ddr_funnel1_out0>;
2002 ddr_tpda_in4: endpoint {
2003 remote-endpoint = <&ddr_tpdm3_out>;
2008 out-ports {
2010 ddr_tpda_out: endpoint {
2011 remote-endpoint = <&ddr_funnel5_in0>;
2018 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2022 clock-names = "apb_pclk";
2024 in-ports {
2026 ddr_funnel5_in0: endpoint {
2027 remote-endpoint = <&ddr_tpda_out>;
2032 out-ports {
2034 ddr_funnel5_out: endpoint {
2035 remote-endpoint = <&dlct0_funnel_in4>;
2042 compatible = "qcom,coresight-tpdm", "arm,primecell";
2046 clock-names = "apb_pclk";
2048 qcom,dsb-element-bits = <32>;
2049 qcom,dsb-msrs-num = <32>;
2051 out-ports {
2053 ddr_tpdm0_out: endpoint {
2054 remote-endpoint = <&ddr_funnel0_in0>;
2061 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2065 clock-names = "apb_pclk";
2067 in-ports {
2069 ddr_funnel0_in0: endpoint {
2070 remote-endpoint = <&ddr_tpdm0_out>;
2075 out-ports {
2077 ddr_funnel0_out0: endpoint {
2078 remote-endpoint = <&ddr_tpda_in0>;
2085 compatible = "qcom,coresight-tpdm", "arm,primecell";
2089 clock-names = "apb_pclk";
2091 qcom,dsb-element-bits = <32>;
2092 qcom,dsb-msrs-num = <32>;
2094 out-ports {
2096 ddr_tpdm1_out: endpoint {
2097 remote-endpoint = <&ddr_funnel1_in0>;
2104 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2108 clock-names = "apb_pclk";
2110 in-ports {
2112 ddr_funnel1_in0: endpoint {
2113 remote-endpoint = <&ddr_tpdm1_out>;
2118 out-ports {
2120 ddr_funnel1_out0: endpoint {
2121 remote-endpoint = <&ddr_tpda_in1>;
2133 clock-names = "apb_pclk";
2135 arm,coresight-loses-context-with-cpu;
2136 qcom,skip-power-up;
2138 out-ports {
2140 etm0_out: endpoint {
2141 remote-endpoint = <&apss_funnel0_in0>;
2153 clock-names = "apb_pclk";
2155 arm,coresight-loses-context-with-cpu;
2156 qcom,skip-power-up;
2158 out-ports {
2160 etm1_out: endpoint {
2161 remote-endpoint = <&apss_funnel0_in1>;
2173 clock-names = "apb_pclk";
2175 arm,coresight-loses-context-with-cpu;
2176 qcom,skip-power-up;
2178 out-ports {
2180 etm2_out: endpoint {
2181 remote-endpoint = <&apss_funnel0_in2>;
2193 clock-names = "apb_pclk";
2195 arm,coresight-loses-context-with-cpu;
2196 qcom,skip-power-up;
2198 out-ports {
2200 etm3_out: endpoint {
2201 remote-endpoint = <&apss_funnel0_in3>;
2213 clock-names = "apb_pclk";
2215 arm,coresight-loses-context-with-cpu;
2216 qcom,skip-power-up;
2218 out-ports {
2220 etm4_out: endpoint {
2221 remote-endpoint = <&apss_funnel0_in4>;
2233 clock-names = "apb_pclk";
2235 arm,coresight-loses-context-with-cpu;
2236 qcom,skip-power-up;
2238 out-ports {
2240 etm5_out: endpoint {
2241 remote-endpoint = <&apss_funnel0_in5>;
2253 clock-names = "apb_pclk";
2255 arm,coresight-loses-context-with-cpu;
2256 qcom,skip-power-up;
2258 out-ports {
2260 etm6_out: endpoint {
2261 remote-endpoint = <&apss_funnel0_in6>;
2273 clock-names = "apb_pclk";
2275 arm,coresight-loses-context-with-cpu;
2276 qcom,skip-power-up;
2278 out-ports {
2280 etm7_out: endpoint {
2281 remote-endpoint = <&apss_funnel0_in7>;
2288 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2292 clock-names = "apb_pclk";
2294 in-ports {
2295 #address-cells = <1>;
2296 #size-cells = <0>;
2301 apss_funnel0_in0: endpoint {
2302 remote-endpoint = <&etm0_out>;
2309 apss_funnel0_in1: endpoint {
2310 remote-endpoint = <&etm1_out>;
2317 apss_funnel0_in2: endpoint {
2318 remote-endpoint = <&etm2_out>;
2325 apss_funnel0_in3: endpoint {
2326 remote-endpoint = <&etm3_out>;
2333 apss_funnel0_in4: endpoint {
2334 remote-endpoint = <&etm4_out>;
2341 apss_funnel0_in5: endpoint {
2342 remote-endpoint = <&etm5_out>;
2349 apss_funnel0_in6: endpoint {
2350 remote-endpoint = <&etm6_out>;
2357 apss_funnel0_in7: endpoint {
2358 remote-endpoint = <&etm7_out>;
2363 out-ports {
2365 apss_funnel0_out: endpoint {
2366 remote-endpoint = <&apss_funnel1_in0>;
2373 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2377 clock-names = "apb_pclk";
2379 in-ports {
2380 #address-cells = <1>;
2381 #size-cells = <0>;
2386 apss_funnel1_in0: endpoint {
2387 remote-endpoint = <&apss_funnel0_out>;
2394 apss_funnel1_in3: endpoint {
2395 remote-endpoint = <&apss_tpda_out>;
2400 out-ports {
2402 apss_funnel1_out: endpoint {
2403 remote-endpoint = <&funnel1_in4>;
2410 compatible = "arm,coresight-cti", "arm,primecell";
2414 clock-names = "apb_pclk";
2418 compatible = "qcom,coresight-tpdm", "arm,primecell";
2422 clock-names = "apb_pclk";
2424 qcom,cmb-element-bits = <64>;
2425 qcom,cmb-msrs-num = <32>;
2427 out-ports {
2429 apss_tpdm3_out: endpoint {
2430 remote-endpoint = <&apss_tpda_in3>;
2437 compatible = "qcom,coresight-tpdm", "arm,primecell";
2441 clock-names = "apb_pclk";
2443 qcom,dsb-element-bits = <32>;
2444 qcom,dsb-msrs-num = <32>;
2446 out-ports {
2448 apss_tpdm4_out: endpoint {
2449 remote-endpoint = <&apss_tpda_in4>;
2456 compatible = "qcom,coresight-tpda", "arm,primecell";
2460 clock-names = "apb_pclk";
2462 in-ports {
2463 #address-cells = <1>;
2464 #size-cells = <0>;
2469 apss_tpda_in0: endpoint {
2470 remote-endpoint = <&apss_tpdm0_out>;
2477 apss_tpda_in1: endpoint {
2478 remote-endpoint = <&apss_tpdm1_out>;
2485 apss_tpda_in2: endpoint {
2486 remote-endpoint = <&apss_tpdm2_out>;
2493 apss_tpda_in3: endpoint {
2494 remote-endpoint = <&apss_tpdm3_out>;
2501 apss_tpda_in4: endpoint {
2502 remote-endpoint = <&apss_tpdm4_out>;
2507 out-ports {
2509 apss_tpda_out: endpoint {
2510 remote-endpoint = <&apss_funnel1_in3>;
2517 compatible = "qcom,coresight-tpdm", "arm,primecell";
2521 clock-names = "apb_pclk";
2523 qcom,cmb-element-bits = <32>;
2524 qcom,cmb-msrs-num = <32>;
2526 out-ports {
2528 apss_tpdm1_out: endpoint {
2529 remote-endpoint = <&apss_tpda_in1>;
2536 compatible = "qcom,coresight-tpdm", "arm,primecell";
2540 clock-names = "apb_pclk";
2542 qcom,cmb-element-bits = <32>;
2543 qcom,cmb-msrs-num = <32>;
2545 out-ports {
2547 apss_tpdm0_out: endpoint {
2548 remote-endpoint = <&apss_tpda_in0>;
2555 compatible = "qcom,coresight-tpdm", "arm,primecell";
2559 clock-names = "apb_pclk";
2561 qcom,dsb-element-bits = <32>;
2562 qcom,dsb-msrs-num = <32>;
2564 out-ports {
2566 apss_tpdm2_out: endpoint {
2567 remote-endpoint = <&apss_tpda_in2>;
2574 compatible = "arm,coresight-cti", "arm,primecell";
2578 clock-names = "apb_pclk";
2582 compatible = "arm,coresight-cti", "arm,primecell";
2586 clock-names = "apb_pclk";
2590 compatible = "arm,coresight-cti", "arm,primecell";
2594 clock-names = "apb_pclk";
2598 compatible = "qcom,qcs8300-usb-hs-phy",
2599 "qcom,usb-snps-hs-7nm-phy";
2603 clock-names = "ref";
2607 #phy-cells = <0>;
2613 compatible = "qcom,qcs8300-usb-hs-phy",
2614 "qcom,usb-snps-hs-7nm-phy";
2618 clock-names = "ref";
2622 #phy-cells = <0>;
2628 compatible = "qcom,qcs8300-qmp-usb3-uni-phy";
2635 clock-names = "aux",
2642 reset-names = "phy", "phy_phy";
2644 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
2646 #clock-cells = <0>;
2647 clock-output-names = "usb3_prim_phy_pipe_clk_src";
2649 #phy-cells = <0>;
2655 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy";
2658 clock-names = "sgmi_ref";
2659 #phy-cells = <0>;
2663 gpucc: clock-controller@3d90000 {
2664 compatible = "qcom,qcs8300-gpucc";
2669 clock-names = "bi_tcxo",
2672 #clock-cells = <1>;
2673 #reset-cells = <1>;
2674 #power-domain-cells = <1>;
2678 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2686 operating-points-v2 = <&llcc_bwmon_opp_table>;
2688 llcc_bwmon_opp_table: opp-table {
2689 compatible = "operating-points-v2";
2691 opp-0 {
2692 opp-peak-kBps = <762000>;
2695 opp-1 {
2696 opp-peak-kBps = <1720000>;
2699 opp-2 {
2700 opp-peak-kBps = <2086000>;
2703 opp-3 {
2704 opp-peak-kBps = <2601000>;
2707 opp-4 {
2708 opp-peak-kBps = <2929000>;
2711 opp-5 {
2712 opp-peak-kBps = <5931000>;
2715 opp-6 {
2716 opp-peak-kBps = <6515000>;
2719 opp-7 {
2720 opp-peak-kBps = <7984000>;
2723 opp-8 {
2724 opp-peak-kBps = <10437000>;
2727 opp-9 {
2728 opp-peak-kBps = <12195000>;
2734 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
2740 operating-points-v2 = <&cpu_bwmon_opp_table>;
2742 cpu_bwmon_opp_table: opp-table {
2743 compatible = "operating-points-v2";
2745 opp-0 {
2746 opp-peak-kBps = <9155000>;
2749 opp-1 {
2750 opp-peak-kBps = <12298000>;
2753 opp-2 {
2754 opp-peak-kBps = <14236000>;
2757 opp-3 {
2758 opp-peak-kBps = <16265000>;
2764 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
2770 operating-points-v2 = <&cpu_bwmon_opp_table>;
2774 compatible = "qcom,qcs8300-dc-noc";
2776 #interconnect-cells = <2>;
2777 qcom,bcm-voters = <&apps_bcm_voter>;
2781 compatible = "qcom,qcs8300-gem-noc";
2783 #interconnect-cells = <2>;
2784 qcom,bcm-voters = <&apps_bcm_voter>;
2787 llcc: system-cache-controller@9200000 {
2788 compatible = "qcom,qcs8300-llcc";
2794 reg-names = "llcc0_base",
2803 compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
2811 clock-names = "cfg_noc",
2817 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2819 assigned-clock-rates = <19200000>, <200000000>;
2821 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
2826 interrupt-names = "pwr_event",
2832 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
2833 required-opps = <&rpmhpd_opp_nom>;
2840 interconnect-names = "usb-ddr", "apps-usb";
2842 wakeup-source;
2844 #address-cells = <2>;
2845 #size-cells = <2>;
2856 phy-names = "usb2-phy", "usb3-phy";
2858 snps,dis-u1-entry-quirk;
2859 snps,dis-u2-entry-quirk;
2866 compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
2874 clock-names = "cfg_noc",
2880 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2882 assigned-clock-rates = <19200000>, <120000000>;
2884 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
2888 interrupt-names = "pwr_event",
2893 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
2894 required-opps = <&rpmhpd_opp_nom>;
2902 interconnect-names = "usb-ddr", "apps-usb";
2904 qcom,select-utmi-as-pipe-clk;
2905 wakeup-source;
2907 #address-cells = <2>;
2908 #size-cells = <2>;
2921 phy-names = "usb2-phy";
2922 maximum-speed = "high-speed";
2924 snps,dis-u1-entry-quirk;
2925 snps,dis-u2-entry-quirk;
2932 videocc: clock-controller@abf0000 {
2933 compatible = "qcom,qcs8300-videocc";
2939 power-domains = <&rpmhpd RPMHPD_MMCX>;
2940 #clock-cells = <1>;
2941 #reset-cells = <1>;
2942 #power-domain-cells = <1>;
2945 camcc: clock-controller@ade0000 {
2946 compatible = "qcom,qcs8300-camcc";
2952 power-domains = <&rpmhpd RPMHPD_MMCX>;
2953 #clock-cells = <1>;
2954 #reset-cells = <1>;
2955 #power-domain-cells = <1>;
2958 dispcc: clock-controller@af00000 {
2959 compatible = "qcom,sa8775p-dispcc0";
2967 power-domains = <&rpmhpd RPMHPD_MMCX>;
2968 #clock-cells = <1>;
2969 #reset-cells = <1>;
2970 #power-domain-cells = <1>;
2973 pdc: interrupt-controller@b220000 {
2974 compatible = "qcom,qcs8300-pdc", "qcom,pdc";
2977 interrupt-parent = <&intc>;
2978 #interrupt-cells = <2>;
2979 interrupt-controller;
2980 qcom,pdc-ranges = <0 480 40>,
3020 aoss_qmp: power-management@c300000 {
3021 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp";
3023 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
3027 #clock-cells = <0>;
3031 compatible = "qcom,qcs8300-tlmm";
3034 gpio-controller;
3035 #gpio-cells = <2>;
3036 gpio-ranges = <&tlmm 0 0 134>;
3037 interrupt-controller;
3038 #interrupt-cells = <2>;
3039 wakeup-parent = <&pdc>;
3041 qup_uart7_default: qup-uart7-state {
3049 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd";
3053 #address-cells = <1>;
3054 #size-cells = <1>;
3056 pil-reloc@94c {
3057 compatible = "qcom,pil-reloc-info";
3063 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3066 #iommu-cells = <2>;
3067 #global-interrupts = <2>;
3068 dma-coherent;
3202 intc: interrupt-controller@17a00000 {
3203 compatible = "arm,gic-v3";
3207 #interrupt-cells = <3>;
3208 interrupt-controller;
3209 #redistributor-regions = <1>;
3210 redistributor-stride = <0x0 0x20000>;
3214 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt";
3221 compatible = "arm,armv7-timer-mem";
3224 #address-cells = <1>;
3225 #size-cells = <1>;
3230 frame-number = <0>;
3237 frame-number = <1>;
3244 frame-number = <2>;
3251 frame-number = <3>;
3258 frame-number = <4>;
3265 frame-number = <5>;
3272 frame-number = <6>;
3279 compatible = "qcom,rpmh-rsc";
3283 reg-names = "drv-0",
3284 "drv-1",
3285 "drv-2";
3290 power-domains = <&system_pd>;
3293 qcom,tcs-offset = <0xd00>;
3294 qcom,drv-id = <2>;
3295 qcom,tcs-config = <ACTIVE_TCS 2>,
3300 apps_bcm_voter: bcm-voter {
3301 compatible = "qcom,bcm-voter";
3304 rpmhcc: clock-controller {
3305 compatible = "qcom,sa8775p-rpmh-clk";
3306 #clock-cells = <1>;
3308 clock-names = "xo";
3311 rpmhpd: power-controller {
3312 compatible = "qcom,qcs8300-rpmhpd";
3313 #power-domain-cells = <1>;
3314 operating-points-v2 = <&rpmhpd_opp_table>;
3316 rpmhpd_opp_table: opp-table {
3317 compatible = "operating-points-v2";
3319 rpmhpd_opp_ret: opp-0 {
3320 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3323 rpmhpd_opp_min_svs: opp-1 {
3324 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3327 rpmhpd_opp_low_svs: opp-2 {
3328 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3331 rpmhpd_opp_svs: opp-3 {
3332 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3335 rpmhpd_opp_svs_l1: opp-4 {
3336 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3339 rpmhpd_opp_nom: opp-5 {
3340 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3343 rpmhpd_opp_nom_l1: opp-6 {
3344 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3347 rpmhpd_opp_nom_l2: opp-7 {
3348 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3351 rpmhpd_opp_turbo: opp-8 {
3352 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3355 rpmhpd_opp_turbo_l1: opp-9 {
3356 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3363 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas";
3366 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
3371 interrupt-names = "wdog",
3375 "stop-ack";
3378 clock-names = "xo";
3380 power-domains = <&rpmhpd RPMHPD_CX>,
3382 power-domain-names = "cx",
3388 memory-region = <&gpdsp_mem>;
3392 qcom,smem-states = <&smp2p_gpdsp_out 0>;
3393 qcom,smem-state-names = "stop";
3397 glink-edge {
3398 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
3405 qcom,remote-pid = <17>;
3410 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos";
3413 reg-names = "stmmaceth", "rgmii";
3417 interrupt-names = "macirq", "sfty";
3423 clock-names = "stmmaceth",
3427 power-domains = <&gcc GCC_EMAC0_GDSC>;
3430 phy-names = "serdes";
3433 dma-coherent;
3437 rx-fifo-depth = <16384>;
3438 tx-fifo-depth = <20480>;
3444 compatible = "qcom,qcs8300-nspa-noc";
3446 #interconnect-cells = <2>;
3447 qcom,bcm-voters = <&apps_bcm_voter>;
3451 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas";
3454 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3459 interrupt-names = "wdog",
3463 "stop-ack";
3466 clock-names = "xo";
3468 power-domains = <&rpmhpd RPMHPD_CX>,
3472 power-domain-names = "cx",
3479 memory-region = <&cdsp_mem>;
3483 qcom,smem-states = <&smp2p_cdsp_out 0>;
3484 qcom,smem-state-names = "stop";
3488 glink-edge {
3489 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3496 qcom,remote-pid = <5>;
3500 qcom,glink-channels = "fastrpcglink-apps-dsp";
3502 #address-cells = <1>;
3503 #size-cells = <0>;
3505 compute-cb@1 {
3506 compatible = "qcom,fastrpc-compute-cb";
3510 dma-coherent;
3513 compute-cb@2 {
3514 compatible = "qcom,fastrpc-compute-cb";
3518 dma-coherent;
3521 compute-cb@3 {
3522 compatible = "qcom,fastrpc-compute-cb";
3526 dma-coherent;
3529 compute-cb@4 {
3530 compatible = "qcom,fastrpc-compute-cb";
3534 dma-coherent;
3542 compatible = "arm,armv8-timer";