Lines Matching +full:opp +full:- +full:384000000
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qcs615-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/interconnect/qcom,icc.h>
10 #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/power/qcom,rpmhpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a55";
29 enable-method = "psci";
30 power-domains = <&cpu_pd0>;
31 power-domain-names = "psci";
32 capacity-dmips-mhz = <1024>;
33 dynamic-power-coefficient = <100>;
34 next-level-cache = <&l2_0>;
35 #cooling-cells = <2>;
37 l2_0: l2-cache {
39 cache-level = <2>;
40 cache-unified;
41 next-level-cache = <&l3_0>;
47 compatible = "arm,cortex-a55";
49 enable-method = "psci";
50 power-domains = <&cpu_pd1>;
51 power-domain-names = "psci";
52 capacity-dmips-mhz = <1024>;
53 dynamic-power-coefficient = <100>;
54 next-level-cache = <&l2_100>;
56 l2_100: l2-cache {
58 cache-level = <2>;
59 cache-unified;
60 next-level-cache = <&l3_0>;
66 compatible = "arm,cortex-a55";
68 enable-method = "psci";
69 power-domains = <&cpu_pd2>;
70 power-domain-names = "psci";
71 capacity-dmips-mhz = <1024>;
72 dynamic-power-coefficient = <100>;
73 next-level-cache = <&l2_200>;
75 l2_200: l2-cache {
77 cache-level = <2>;
78 cache-unified;
79 next-level-cache = <&l3_0>;
85 compatible = "arm,cortex-a55";
87 enable-method = "psci";
88 power-domains = <&cpu_pd3>;
89 power-domain-names = "psci";
90 capacity-dmips-mhz = <1024>;
91 dynamic-power-coefficient = <100>;
92 next-level-cache = <&l2_300>;
94 l2_300: l2-cache {
96 cache-level = <2>;
97 cache-unified;
98 next-level-cache = <&l3_0>;
104 compatible = "arm,cortex-a55";
106 enable-method = "psci";
107 power-domains = <&cpu_pd4>;
108 power-domain-names = "psci";
109 capacity-dmips-mhz = <1024>;
110 dynamic-power-coefficient = <100>;
111 next-level-cache = <&l2_400>;
113 l2_400: l2-cache {
115 cache-level = <2>;
116 cache-unified;
117 next-level-cache = <&l3_0>;
123 compatible = "arm,cortex-a55";
125 enable-method = "psci";
126 power-domains = <&cpu_pd5>;
127 power-domain-names = "psci";
128 capacity-dmips-mhz = <1024>;
129 dynamic-power-coefficient = <100>;
130 next-level-cache = <&l2_500>;
132 l2_500: l2-cache {
134 cache-level = <2>;
135 cache-unified;
136 next-level-cache = <&l3_0>;
142 compatible = "arm,cortex-a76";
144 enable-method = "psci";
145 power-domains = <&cpu_pd6>;
146 power-domain-names = "psci";
147 capacity-dmips-mhz = <1740>;
148 dynamic-power-coefficient = <404>;
149 next-level-cache = <&l2_600>;
150 #cooling-cells = <2>;
152 l2_600: l2-cache {
154 cache-level = <2>;
155 cache-unified;
156 next-level-cache = <&l3_0>;
162 compatible = "arm,cortex-a76";
164 enable-method = "psci";
165 power-domains = <&cpu_pd7>;
166 power-domain-names = "psci";
167 capacity-dmips-mhz = <1740>;
168 dynamic-power-coefficient = <404>;
169 next-level-cache = <&l2_700>;
171 l2_700: l2-cache {
173 cache-level = <2>;
174 cache-unified;
175 next-level-cache = <&l3_0>;
179 cpu-map {
215 l3_0: l3-cache {
217 cache-level = <3>;
218 cache-unified;
222 dummy_eud: dummy-sink {
223 compatible = "arm,coresight-dummy-sink";
225 in-ports {
228 remote-endpoint = <&replicator_swao_out1>;
234 idle-states {
235 entry-method = "psci";
237 little_cpu_sleep_0: cpu-sleep-0-0 {
238 compatible = "arm,idle-state";
239 idle-state-name = "silver-power-collapse";
240 arm,psci-suspend-param = <0x40000003>;
241 entry-latency-us = <549>;
242 exit-latency-us = <901>;
243 min-residency-us = <1774>;
244 local-timer-stop;
247 little_cpu_sleep_1: cpu-sleep-0-1 {
248 compatible = "arm,idle-state";
249 idle-state-name = "silver-rail-power-collapse";
250 arm,psci-suspend-param = <0x40000004>;
251 entry-latency-us = <702>;
252 exit-latency-us = <915>;
253 min-residency-us = <4001>;
254 local-timer-stop;
257 big_cpu_sleep_0: cpu-sleep-1-0 {
258 compatible = "arm,idle-state";
259 idle-state-name = "gold-power-collapse";
260 arm,psci-suspend-param = <0x40000003>;
261 entry-latency-us = <523>;
262 exit-latency-us = <1244>;
263 min-residency-us = <2207>;
264 local-timer-stop;
267 big_cpu_sleep_1: cpu-sleep-1-1 {
268 compatible = "arm,idle-state";
269 idle-state-name = "gold-rail-power-collapse";
270 arm,psci-suspend-param = <0x40000004>;
271 entry-latency-us = <526>;
272 exit-latency-us = <1854>;
273 min-residency-us = <5555>;
274 local-timer-stop;
278 domain-idle-states {
279 cluster_sleep_0: cluster-sleep-0 {
280 compatible = "domain-idle-state";
281 arm,psci-suspend-param = <0x41000044>;
282 entry-latency-us = <2752>;
283 exit-latency-us = <3048>;
284 min-residency-us = <6118>;
287 cluster_sleep_1: cluster-sleep-1 {
288 compatible = "domain-idle-state";
289 arm,psci-suspend-param = <0x41001344>;
290 entry-latency-us = <3263>;
291 exit-latency-us = <4562>;
292 min-residency-us = <8467>;
295 cluster_sleep_2: cluster-sleep-2 {
296 compatible = "domain-idle-state";
297 arm,psci-suspend-param = <0x4100b344>;
298 entry-latency-us = <3638>;
299 exit-latency-us = <6562>;
300 min-residency-us = <9826>;
312 compatible = "qcom,scm-qcs615", "qcom,scm";
313 qcom,dload-mode = <&tcsr 0x13000>;
317 camnoc_virt: interconnect-0 {
318 compatible = "qcom,qcs615-camnoc-virt";
319 #interconnect-cells = <2>;
320 qcom,bcm-voters = <&apps_bcm_voter>;
323 ipa_virt: interconnect-1 {
324 compatible = "qcom,qcs615-ipa-virt";
325 #interconnect-cells = <2>;
326 qcom,bcm-voters = <&apps_bcm_voter>;
329 mc_virt: interconnect-2 {
330 compatible = "qcom,qcs615-mc-virt";
331 #interconnect-cells = <2>;
332 qcom,bcm-voters = <&apps_bcm_voter>;
335 qup_opp_table: opp-table-qup {
336 compatible = "operating-points-v2";
337 opp-shared;
339 opp-75000000 {
340 opp-hz = /bits/ 64 <75000000>;
341 required-opps = <&rpmhpd_opp_low_svs>;
344 opp-100000000 {
345 opp-hz = /bits/ 64 <100000000>;
346 required-opps = <&rpmhpd_opp_svs>;
349 opp-128000000 {
350 opp-hz = /bits/ 64 <128000000>;
351 required-opps = <&rpmhpd_opp_nom>;
356 compatible = "arm,psci-1.0";
359 cpu_pd0: power-domain-cpu0 {
360 #power-domain-cells = <0>;
361 power-domains = <&cluster_pd>;
362 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
365 cpu_pd1: power-domain-cpu1 {
366 #power-domain-cells = <0>;
367 power-domains = <&cluster_pd>;
368 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
371 cpu_pd2: power-domain-cpu2 {
372 #power-domain-cells = <0>;
373 power-domains = <&cluster_pd>;
374 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
377 cpu_pd3: power-domain-cpu3 {
378 #power-domain-cells = <0>;
379 power-domains = <&cluster_pd>;
380 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
383 cpu_pd4: power-domain-cpu4 {
384 #power-domain-cells = <0>;
385 power-domains = <&cluster_pd>;
386 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
389 cpu_pd5: power-domain-cpu5 {
390 #power-domain-cells = <0>;
391 power-domains = <&cluster_pd>;
392 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
395 cpu_pd6: power-domain-cpu6 {
396 #power-domain-cells = <0>;
397 power-domains = <&cluster_pd>;
398 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
401 cpu_pd7: power-domain-cpu7 {
402 #power-domain-cells = <0>;
403 power-domains = <&cluster_pd>;
404 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
407 cluster_pd: power-domain-cluster {
408 #power-domain-cells = <0>;
409 domain-idle-states = <&cluster_sleep_0
415 reserved-memory {
416 #address-cells = <2>;
417 #size-cells = <2>;
423 no-map;
429 compatible = "simple-bus";
431 dma-ranges = <0 0 0 0 0x10 0>;
432 #address-cells = <2>;
433 #size-cells = <2>;
435 gcc: clock-controller@100000 {
436 compatible = "qcom,qcs615-gcc";
439 #clock-cells = <1>;
440 #reset-cells = <1>;
441 #power-domain-cells = <1>;
445 compatible = "qcom,qcs615-qfprom", "qcom,qfprom";
447 #address-cells = <1>;
448 #size-cells = <1>;
450 qusb2_hstx_trim: hstx-trim@1f8 {
457 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
461 reg-names = "hc",
467 interrupt-names = "hc_irq",
474 clock-names = "iface",
481 power-domains = <&rpmhpd RPMHPD_CX>;
482 operating-points-v2 = <&sdhc1_opp_table>;
488 interconnect-names = "sdhc-ddr",
489 "cpu-sdhc";
491 qcom,dll-config = <0x000f642c>;
492 qcom,ddr-config = <0x80040868>;
493 supports-cqe;
494 dma-coherent;
498 sdhc1_opp_table: opp-table {
499 compatible = "operating-points-v2";
501 opp-50000000 {
502 opp-hz = /bits/ 64 <50000000>;
503 required-opps = <&rpmhpd_opp_low_svs>;
506 opp-100000000 {
507 opp-hz = /bits/ 64 <100000000>;
508 required-opps = <&rpmhpd_opp_svs>;
511 opp-200000000 {
512 opp-hz = /bits/ 64 <200000000>;
513 required-opps = <&rpmhpd_opp_svs_l1>;
516 opp-384000000 {
517 opp-hz = /bits/ 64 <384000000>;
518 required-opps = <&rpmhpd_opp_nom>;
523 gpi_dma0: dma-controller@800000 {
524 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
526 #dma-cells = <3>;
535 dma-channels = <8>;
536 dma-channel-mask = <0xf>;
542 compatible = "qcom,geni-se-qup";
547 clock-names = "m-ahb",
548 "s-ahb";
550 #address-cells = <2>;
551 #size-cells = <2>;
555 compatible = "qcom,geni-debug-uart";
558 clock-names = "se";
559 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>;
560 pinctrl-names = "default";
566 interconnect-names = "qup-core",
567 "qup-config";
568 power-domains = <&rpmhpd RPMHPD_CX>;
573 compatible = "qcom,geni-i2c";
575 #address-cells = <1>;
576 #size-cells = <0>;
579 clock-names = "se";
580 pinctrl-0 = <&qup_i2c1_data_clk>;
581 pinctrl-names = "default";
588 interconnect-names = "qup-core",
589 "qup-config",
590 "qup-memory";
591 power-domains = <&rpmhpd RPMHPD_CX>;
594 dma-names = "tx",
600 compatible = "qcom,geni-i2c";
602 #address-cells = <1>;
603 #size-cells = <0>;
606 clock-names = "se";
607 pinctrl-0 = <&qup_i2c2_data_clk>;
608 pinctrl-names = "default";
615 interconnect-names = "qup-core",
616 "qup-config",
617 "qup-memory";
618 power-domains = <&rpmhpd RPMHPD_CX>;
621 dma-names = "tx",
627 compatible = "qcom,geni-spi";
631 clock-names = "se";
632 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
633 pinctrl-names = "default";
638 interconnect-names = "qup-core",
639 "qup-config";
640 power-domains = <&rpmhpd RPMHPD_CX>;
643 dma-names = "tx",
645 #address-cells = <1>;
646 #size-cells = <0>;
651 compatible = "qcom,geni-uart";
655 clock-names = "se";
656 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
658 pinctrl-names = "default";
663 interconnect-names = "qup-core",
664 "qup-config";
665 power-domains = <&rpmhpd RPMHPD_CX>;
670 compatible = "qcom,geni-i2c";
672 #address-cells = <1>;
673 #size-cells = <0>;
676 clock-names = "se";
677 pinctrl-0 = <&qup_i2c3_data_clk>;
678 pinctrl-names = "default";
685 interconnect-names = "qup-core",
686 "qup-config",
687 "qup-memory";
688 power-domains = <&rpmhpd RPMHPD_CX>;
691 dma-names = "tx",
697 gpi_dma1: dma-controller@a00000 {
698 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
700 #dma-cells = <3>;
709 dma-channels = <8>;
710 dma-channel-mask = <0xf>;
716 compatible = "qcom,geni-se-qup";
721 clock-names = "m-ahb",
722 "s-ahb";
724 #address-cells = <2>;
725 #size-cells = <2>;
729 compatible = "qcom,geni-i2c";
732 clock-names = "se";
733 pinctrl-0 = <&qup_i2c4_data_clk>;
734 pinctrl-names = "default";
736 #address-cells = <1>;
737 #size-cells = <0>;
744 interconnect-names = "qup-core",
745 "qup-config",
746 "qup-memory";
747 power-domains = <&rpmhpd RPMHPD_CX>;
748 required-opps = <&rpmhpd_opp_low_svs>;
751 dma-names = "tx",
757 compatible = "qcom,geni-spi";
760 clock-names = "se";
761 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
762 pinctrl-names = "default";
764 #address-cells = <1>;
765 #size-cells = <0>;
770 interconnect-names = "qup-core",
771 "qup-config";
772 power-domains = <&rpmhpd RPMHPD_CX>;
773 operating-points-v2 = <&qup_opp_table>;
776 dma-names = "tx",
782 compatible = "qcom,geni-uart";
785 clock-names = "se";
786 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
788 pinctrl-names = "default";
794 interconnect-names = "qup-core",
795 "qup-config";
796 power-domains = <&rpmhpd RPMHPD_CX>;
797 operating-points-v2 = <&qup_opp_table>;
802 compatible = "qcom,geni-i2c";
805 clock-names = "se";
806 pinctrl-0 = <&qup_i2c5_data_clk>;
807 pinctrl-names = "default";
809 #address-cells = <1>;
810 #size-cells = <0>;
817 interconnect-names = "qup-core",
818 "qup-config",
819 "qup-memory";
820 power-domains = <&rpmhpd RPMHPD_CX>;
821 required-opps = <&rpmhpd_opp_low_svs>;
824 dma-names = "tx",
830 compatible = "qcom,geni-i2c";
833 clock-names = "se";
834 pinctrl-0 = <&qup_i2c6_data_clk>;
835 pinctrl-names = "default";
837 #address-cells = <1>;
838 #size-cells = <0>;
845 interconnect-names = "qup-core",
846 "qup-config",
847 "qup-memory";
848 power-domains = <&rpmhpd RPMHPD_CX>;
849 required-opps = <&rpmhpd_opp_low_svs>;
852 dma-names = "tx",
858 compatible = "qcom,geni-spi";
861 clock-names = "se";
862 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
863 pinctrl-names = "default";
865 #address-cells = <1>;
866 #size-cells = <0>;
871 interconnect-names = "qup-core",
872 "qup-config";
873 power-domains = <&rpmhpd RPMHPD_CX>;
874 operating-points-v2 = <&qup_opp_table>;
877 dma-names = "tx",
883 compatible = "qcom,geni-uart";
886 clock-names = "se";
887 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
889 pinctrl-names = "default";
895 interconnect-names = "qup-core",
896 "qup-config";
897 power-domains = <&rpmhpd RPMHPD_CX>;
898 operating-points-v2 = <&qup_opp_table>;
903 compatible = "qcom,geni-i2c";
906 clock-names = "se";
907 pinctrl-0 = <&qup_i2c7_data_clk>;
908 pinctrl-names = "default";
910 #address-cells = <1>;
911 #size-cells = <0>;
918 interconnect-names = "qup-core",
919 "qup-config",
920 "qup-memory";
921 power-domains = <&rpmhpd RPMHPD_CX>;
922 required-opps = <&rpmhpd_opp_low_svs>;
925 dma-names = "tx",
931 compatible = "qcom,geni-spi";
934 clock-names = "se";
935 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
936 pinctrl-names = "default";
938 #address-cells = <1>;
939 #size-cells = <0>;
944 interconnect-names = "qup-core",
945 "qup-config";
946 power-domains = <&rpmhpd RPMHPD_CX>;
947 operating-points-v2 = <&qup_opp_table>;
950 dma-names = "tx",
956 compatible = "qcom,geni-uart";
959 clock-names = "se";
960 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>,
962 pinctrl-names = "default";
968 interconnect-names = "qup-core",
969 "qup-config";
970 power-domains = <&rpmhpd RPMHPD_CX>;
971 operating-points-v2 = <&qup_opp_table>;
978 compatible = "qcom,qcs615-config-noc";
979 #interconnect-cells = <2>;
980 qcom,bcm-voters = <&apps_bcm_voter>;
985 compatible = "qcom,qcs615-system-noc";
986 #interconnect-cells = <2>;
987 qcom,bcm-voters = <&apps_bcm_voter>;
992 compatible = "qcom,qcs615-aggre1-noc";
993 #interconnect-cells = <2>;
994 qcom,bcm-voters = <&apps_bcm_voter>;
999 compatible = "qcom,qcs615-mmss-noc";
1000 #interconnect-cells = <2>;
1001 qcom,bcm-voters = <&apps_bcm_voter>;
1005 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1008 reg-names = "std",
1021 clock-names = "core_clk",
1031 reset-names = "rst";
1033 operating-points-v2 = <&ufs_opp_table>;
1038 interconnect-names = "ufs-ddr",
1039 "cpu-ufs";
1041 power-domains = <&gcc UFS_PHY_GDSC>;
1044 dma-coherent;
1046 lanes-per-direction = <1>;
1049 phy-names = "ufsphy";
1051 #reset-cells = <1>;
1055 ufs_opp_table: opp-table {
1056 compatible = "operating-points-v2";
1058 opp-50000000 {
1059 opp-hz = /bits/ 64 <50000000>,
1067 required-opps = <&rpmhpd_opp_low_svs>;
1070 opp-100000000 {
1071 opp-hz = /bits/ 64 <100000000>,
1079 required-opps = <&rpmhpd_opp_svs>;
1082 opp-200000000 {
1083 opp-hz = /bits/ 64 <200000000>,
1091 required-opps = <&rpmhpd_opp_nom>;
1097 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy";
1102 clock-names = "ref",
1106 power-domains = <&gcc UFS_PHY_GDSC>;
1109 reset-names = "ufsphy";
1111 #clock-cells = <1>;
1112 #phy-cells = <0>;
1118 compatible = "qcom,tcsr-mutex";
1120 #hwlock-cells = <1>;
1124 compatible = "qcom,qcs615-tcsr", "syscon";
1129 compatible = "qcom,qcs615-tlmm";
1133 reg-names = "east",
1137 gpio-ranges = <&tlmm 0 0 124>;
1138 gpio-controller;
1139 #gpio-cells = <2>;
1140 interrupt-controller;
1141 #interrupt-cells = <2>;
1142 wakeup-parent = <&pdc>;
1144 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
1150 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1155 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1160 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
1165 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1170 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1175 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
1180 qup_spi2_data_clk: qup-spi2-data-clk-state {
1185 qup_spi2_cs: qup-spi2-cs-state {
1190 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
1195 qup_spi4_data_clk: qup-spi4-data-clk-state {
1200 qup_spi4_cs: qup-spi4-cs-state {
1205 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
1210 qup_spi6_data_clk: qup-spi6-data-clk-state {
1215 qup_spi6_cs: qup-spi6-cs-state {
1220 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1225 qup_spi7_data_clk: qup-spi7-data-clk-state {
1230 qup_spi7_cs: qup-spi7-cs-state {
1235 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
1240 qup_uart0_tx: qup-uart0-tx-state {
1245 qup_uart0_rx: qup-uart0-rx-state {
1250 qup_uart2_cts: qup-uart2-cts-state {
1255 qup_uart2_rts: qup-uart2-rts-state {
1260 qup_uart2_tx: qup-uart2-tx-state {
1265 qup_uart2_rx: qup-uart2-rx-state {
1270 qup_uart4_cts: qup-uart4-cts-state {
1275 qup_uart4_rts: qup-uart4-rts-state {
1280 qup_uart4_tx: qup-uart4-tx-state {
1285 qup_uart4_rx: qup-uart4-rx-state {
1290 qup_uart6_cts: qup-uart6-cts-state {
1295 qup_uart6_rts: qup-uart6-rts-state {
1300 qup_uart6_tx: qup-uart6-tx-state {
1305 qup_uart6_rx: qup-uart6-rx-state {
1310 qup_uart7_cts: qup-uart7-cts-state {
1315 qup_uart7_rts: qup-uart7-rts-state {
1320 qup_uart7_tx: qup-uart7-tx-state {
1325 qup_uart7_rx: qup-uart7-rx-state {
1330 sdc1_state_on: sdc1-on-state {
1331 clk-pins {
1333 bias-disable;
1334 drive-strength = <16>;
1337 cmd-pins {
1339 bias-pull-up;
1340 drive-strength = <10>;
1343 data-pins {
1345 bias-pull-up;
1346 drive-strength = <10>;
1349 rclk-pins {
1351 bias-pull-down;
1355 sdc1_state_off: sdc1-off-state {
1356 clk-pins {
1358 bias-disable;
1359 drive-strength = <2>;
1362 cmd-pins {
1364 bias-pull-up;
1365 drive-strength = <2>;
1368 data-pins {
1370 bias-pull-up;
1371 drive-strength = <2>;
1374 rclk-pins {
1376 bias-pull-down;
1380 sdc2_state_on: sdc2-on-state {
1381 clk-pins {
1383 bias-disable;
1384 drive-strength = <16>;
1387 cmd-pins {
1389 bias-pull-up;
1390 drive-strength = <10>;
1393 data-pins {
1395 bias-pull-up;
1396 drive-strength = <10>;
1400 sdc2_state_off: sdc2-off-state {
1401 clk-pins {
1403 bias-disable;
1404 drive-strength = <2>;
1407 cmd-pins {
1409 bias-pull-up;
1410 drive-strength = <2>;
1413 data-pins {
1415 bias-pull-up;
1416 drive-strength = <2>;
1422 compatible = "arm,coresight-stm", "arm,primecell";
1425 reg-names = "stm-base",
1426 "stm-stimulus-base";
1429 clock-names = "apb_pclk";
1431 out-ports {
1434 remote-endpoint = <&funnel_in0_in7>;
1441 compatible = "qcom,coresight-tpda", "arm,primecell";
1445 clock-names = "apb_pclk";
1447 in-ports {
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1455 remote-endpoint = <&tpdm_center_out>;
1463 remote-endpoint = <&funnel_monaq_out>;
1471 remote-endpoint = <&funnel_ddr_0_out>;
1479 remote-endpoint = <&funnel_turing_out>;
1487 remote-endpoint = <&tpdm_vsense_out>;
1495 remote-endpoint = <&tpdm_dcc_out>;
1503 remote-endpoint = <&tpdm_prng_out>;
1511 remote-endpoint = <&tpdm_qm_out>;
1519 remote-endpoint = <&tpdm_west_out>;
1527 remote-endpoint = <&tpdm_pimem_out>;
1532 out-ports {
1535 remote-endpoint = <&funnel_qatb_in>;
1542 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1546 clock-names = "apb_pclk";
1548 in-ports {
1551 remote-endpoint = <&tpda_qdss_out>;
1556 out-ports {
1559 remote-endpoint = <&funnel_in0_in6>;
1566 compatible = "arm,coresight-cti", "arm,primecell";
1570 clock-names = "apb_pclk";
1574 compatible = "arm,coresight-cti", "arm,primecell";
1578 clock-names = "apb_pclk";
1582 compatible = "arm,coresight-cti", "arm,primecell";
1586 clock-names = "apb_pclk";
1590 compatible = "arm,coresight-cti", "arm,primecell";
1594 clock-names = "apb_pclk";
1598 compatible = "arm,coresight-cti", "arm,primecell";
1602 clock-names = "apb_pclk";
1606 compatible = "arm,coresight-cti", "arm,primecell";
1610 clock-names = "apb_pclk";
1614 compatible = "arm,coresight-cti", "arm,primecell";
1618 clock-names = "apb_pclk";
1622 compatible = "arm,coresight-cti", "arm,primecell";
1626 clock-names = "apb_pclk";
1630 compatible = "arm,coresight-cti", "arm,primecell";
1634 clock-names = "apb_pclk";
1638 compatible = "arm,coresight-cti", "arm,primecell";
1642 clock-names = "apb_pclk";
1646 compatible = "arm,coresight-cti", "arm,primecell";
1650 clock-names = "apb_pclk";
1654 compatible = "arm,coresight-cti", "arm,primecell";
1658 clock-names = "apb_pclk";
1662 compatible = "arm,coresight-cti", "arm,primecell";
1666 clock-names = "apb_pclk";
1670 compatible = "arm,coresight-cti", "arm,primecell";
1674 clock-names = "apb_pclk";
1678 compatible = "arm,coresight-cti", "arm,primecell";
1682 clock-names = "apb_pclk";
1686 compatible = "arm,coresight-cti", "arm,primecell";
1690 clock-names = "apb_pclk";
1694 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1698 clock-names = "apb_pclk";
1700 in-ports {
1701 #address-cells = <1>;
1702 #size-cells = <0>;
1708 remote-endpoint = <&funnel_qatb_out>;
1716 remote-endpoint = <&stm_out>;
1721 out-ports {
1724 remote-endpoint = <&funnel_merg_in0>;
1731 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1735 clock-names = "apb_pclk";
1737 in-ports {
1738 #address-cells = <1>;
1739 #size-cells = <0>;
1745 remote-endpoint = <&replicator_swao_out0>;
1753 remote-endpoint = <&tpdm_wcss_out>;
1761 remote-endpoint = <&funnel_apss_merg_out>;
1766 out-ports {
1769 remote-endpoint = <&funnel_merg_in1>;
1776 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1780 clock-names = "apb_pclk";
1782 in-ports {
1783 #address-cells = <1>;
1784 #size-cells = <0>;
1790 remote-endpoint = <&funnel_in0_out>;
1798 remote-endpoint = <&funnel_in1_out>;
1803 out-ports {
1806 remote-endpoint = <&tmc_etf_in>;
1813 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1817 clock-names = "apb_pclk";
1819 in-ports {
1822 remote-endpoint= <&tmc_etf_out>;
1827 out-ports {
1828 #address-cells = <1>;
1829 #size-cells = <0>;
1835 remote-endpoint= <&replicator1_in>;
1842 compatible = "arm,coresight-tmc", "arm,primecell";
1846 clock-names = "apb_pclk";
1848 in-ports {
1851 remote-endpoint = <&funnel_merg_out>;
1856 out-ports {
1859 remote-endpoint = <&replicator0_in>;
1866 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1870 clock-names = "apb_pclk";
1872 in-ports {
1875 remote-endpoint= <&replicator0_out1>;
1880 out-ports {
1883 remote-endpoint= <&funnel_swao_in6>;
1890 compatible = "arm,coresight-cti", "arm,primecell";
1894 clock-names = "apb_pclk";
1898 compatible = "qcom,coresight-tpdm", "arm,primecell";
1902 clock-names = "apb_pclk";
1904 qcom,cmb-element-bits = <64>;
1905 qcom,cmb-msrs-num = <32>;
1908 out-ports {
1911 remote-endpoint = <&tpda_qdss_in7>;
1918 compatible = "qcom,coresight-tpdm", "arm,primecell";
1922 clock-names = "apb_pclk";
1924 qcom,cmb-element-bits = <32>;
1925 qcom,cmb-msrs-num = <32>;
1927 out-ports {
1930 remote-endpoint = <&tpda_qdss_in9>;
1937 compatible = "qcom,coresight-tpdm", "arm,primecell";
1941 clock-names = "apb_pclk";
1943 qcom,cmb-element-bits = <64>;
1944 qcom,cmb-msrs-num = <32>;
1945 qcom,dsb-element-bits = <32>;
1946 qcom,dsb-msrs-num = <32>;
1948 out-ports {
1951 remote-endpoint = <&tpda_qdss_in13>;
1958 compatible = "qcom,coresight-tpdm", "arm,primecell";
1962 clock-names = "apb_pclk";
1964 qcom,dsb-element-bits = <32>;
1965 qcom,dsb-msrs-num = <32>;
1967 out-ports {
1970 remote-endpoint = <&funnel_turing_in>;
1977 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1981 clock-names = "apb_pclk";
1983 in-ports {
1986 remote-endpoint = <&tpdm_turing_out>;
1991 out-ports {
1994 remote-endpoint = <&tpda_qdss_in6>;
2001 compatible = "arm,coresight-cti", "arm,primecell";
2005 clock-names = "apb_pclk";
2009 compatible = "qcom,coresight-tpdm", "arm,primecell";
2013 clock-names = "apb_pclk";
2015 qcom,cmb-element-bits = <32>;
2016 qcom,cmb-msrs-num = <32>;
2019 out-ports {
2022 remote-endpoint = <&tpda_qdss_in8>;
2029 compatible = "qcom,coresight-tpdm", "arm,primecell";
2033 clock-names = "apb_pclk";
2035 qcom,cmb-element-bits = <32>;
2036 qcom,cmb-msrs-num = <32>;
2037 qcom,dsb-element-bits = <32>;
2038 qcom,dsb-msrs-num = <32>;
2041 out-ports {
2044 remote-endpoint = <&funnel_in1_in4>;
2051 compatible = "qcom,coresight-tpdm", "arm,primecell";
2055 clock-names = "apb_pclk";
2057 qcom,dsb-element-bits = <32>;
2058 qcom,dsb-msrs-num = <32>;
2060 out-ports {
2063 remote-endpoint = <&funnel_monaq_in>;
2070 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2074 clock-names = "apb_pclk";
2076 in-ports {
2079 remote-endpoint = <&tpdm_monaq_out>;
2084 out-ports {
2087 remote-endpoint = <&tpda_qdss_in4>;
2094 compatible = "qcom,coresight-tpdm", "arm,primecell";
2098 clock-names = "apb_pclk";
2100 qcom,dsb-element-bits = <32>;
2101 qcom,dsb-msrs-num = <32>;
2104 out-ports {
2107 remote-endpoint = <&tpda_qdss_in11>;
2114 compatible = "qcom,coresight-tpdm", "arm,primecell";
2118 clock-names = "apb_pclk";
2120 qcom,dsb-element-bits = <32>;
2121 qcom,dsb-msrs-num = <32>;
2124 out-ports {
2127 remote-endpoint = <&funnel_ddr_0_in>;
2134 compatible = "arm,coresight-cti", "arm,primecell";
2138 clock-names = "apb_pclk";
2142 compatible = "arm,coresight-cti", "arm,primecell";
2146 clock-names = "apb_pclk";
2150 compatible = "arm,coresight-cti", "arm,primecell";
2154 clock-names = "apb_pclk";
2158 compatible = "arm,coresight-cti", "arm,primecell";
2162 clock-names = "apb_pclk";
2166 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2170 clock-names = "apb_pclk";
2172 in-ports {
2175 remote-endpoint = <&tpdm_ddr_out>;
2180 out-ports {
2183 remote-endpoint = <&tpda_qdss_in5>;
2190 compatible = "qcom,coresight-tpda", "arm,primecell";
2194 clock-names = "apb_pclk";
2196 in-ports {
2197 #address-cells = <1>;
2198 #size-cells = <0>;
2204 remote-endpoint = <&tpdm_swao0_out>;
2212 remote-endpoint = <&tpdm_swao1_out>;
2218 out-ports {
2221 remote-endpoint = <&funnel_swao_in7>;
2228 compatible = "qcom,coresight-tpdm", "arm,primecell";
2232 clock-names = "apb_pclk";
2234 qcom,cmb-element-bits = <64>;
2235 qcom,cmb-msrs-num = <32>;
2238 out-ports {
2241 remote-endpoint = <&tpda_swao_in0>;
2248 compatible = "qcom,coresight-tpdm", "arm,primecell";
2252 clock-names = "apb_pclk";
2254 qcom,dsb-element-bits = <32>;
2255 qcom,dsb-msrs-num = <32>;
2258 out-ports {
2261 remote-endpoint = <&tpda_swao_in1>;
2268 compatible = "arm,coresight-cti", "arm,primecell";
2272 clock-names = "apb_pclk";
2276 compatible = "arm,coresight-cti", "arm,primecell";
2280 clock-names = "apb_pclk";
2284 compatible = "arm,coresight-cti", "arm,primecell";
2288 clock-names = "apb_pclk";
2292 compatible = "arm,coresight-cti", "arm,primecell";
2296 clock-names = "apb_pclk";
2300 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2304 clock-names = "apb_pclk";
2306 in-ports {
2307 #address-cells = <1>;
2308 #size-cells = <0>;
2314 remote-endpoint= <&replicator1_out>;
2322 remote-endpoint= <&tpda_swao_out>;
2327 out-ports {
2330 remote-endpoint = <&tmc_etf_swao_in>;
2337 compatible = "arm,coresight-tmc", "arm,primecell";
2341 clock-names = "apb_pclk";
2343 in-ports {
2346 remote-endpoint= <&funnel_swao_out>;
2351 out-ports {
2354 remote-endpoint= <&replicator_swao_in>;
2361 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2365 clock-names = "apb_pclk";
2367 in-ports {
2370 remote-endpoint = <&tmc_etf_swao_out>;
2375 out-ports {
2376 #address-cells = <1>;
2377 #size-cells = <0>;
2383 remote-endpoint = <&funnel_in1_in3>;
2391 remote-endpoint = <&eud_in>;
2398 compatible = "arm,coresight-cti", "arm,primecell";
2402 clock-names = "apb_pclk";
2406 compatible = "qcom,coresight-tpdm", "arm,primecell";
2410 clock-names = "apb_pclk";
2412 qcom,dsb-element-bits = <32>;
2413 qcom,dsb-msrs-num = <32>;
2415 out-ports {
2418 remote-endpoint = <&tpda_qdss_in12>;
2425 compatible = "arm,coresight-cti", "arm,primecell";
2429 clock-names = "apb_pclk";
2433 compatible = "arm,coresight-cti", "arm,primecell";
2437 clock-names = "apb_pclk";
2442 compatible = "qcom,coresight-tpdm", "arm,primecell";
2446 clock-names = "apb_pclk";
2448 qcom,dsb-element-bits = <32>;
2449 qcom,dsb-msrs-num = <32>;
2451 out-ports {
2454 remote-endpoint = <&tpda_qdss_in0>;
2461 compatible = "arm,coresight-cti", "arm,primecell";
2465 clock-names = "apb_pclk";
2469 compatible = "arm,coresight-cti", "arm,primecell";
2473 clock-names = "apb_pclk";
2477 compatible = "arm,coresight-cti", "arm,primecell";
2481 clock-names = "apb_pclk";
2490 clock-names = "apb_pclk";
2492 arm,coresight-loses-context-with-cpu;
2493 qcom,skip-power-up;
2495 out-ports {
2498 remote-endpoint = <&funnel_apss_in0>;
2505 compatible = "arm,coresight-cti", "arm,primecell";
2509 clock-names = "apb_pclk";
2518 clock-names = "apb_pclk";
2520 arm,coresight-loses-context-with-cpu;
2521 qcom,skip-power-up;
2523 out-ports {
2526 remote-endpoint = <&funnel_apss_in1>;
2533 compatible = "arm,coresight-cti", "arm,primecell";
2537 clock-names = "apb_pclk";
2546 clock-names = "apb_pclk";
2548 arm,coresight-loses-context-with-cpu;
2549 qcom,skip-power-up;
2551 out-ports {
2554 remote-endpoint = <&funnel_apss_in2>;
2561 compatible = "arm,coresight-cti", "arm,primecell";
2565 clock-names = "apb_pclk";
2574 clock-names = "apb_pclk";
2576 arm,coresight-loses-context-with-cpu;
2577 qcom,skip-power-up;
2579 out-ports {
2582 remote-endpoint = <&funnel_apss_in3>;
2589 compatible = "arm,coresight-cti", "arm,primecell";
2593 clock-names = "apb_pclk";
2602 clock-names = "apb_pclk";
2604 arm,coresight-loses-context-with-cpu;
2605 qcom,skip-power-up;
2607 out-ports {
2610 remote-endpoint = <&funnel_apss_in4>;
2617 compatible = "arm,coresight-cti", "arm,primecell";
2621 clock-names = "apb_pclk";
2630 clock-names = "apb_pclk";
2632 arm,coresight-loses-context-with-cpu;
2633 qcom,skip-power-up;
2635 out-ports {
2638 remote-endpoint = <&funnel_apss_in5>;
2645 compatible = "arm,coresight-cti", "arm,primecell";
2649 clock-names = "apb_pclk";
2658 clock-names = "apb_pclk";
2660 arm,coresight-loses-context-with-cpu;
2661 qcom,skip-power-up;
2663 out-ports {
2666 remote-endpoint = <&funnel_apss_in6>;
2673 compatible = "arm,coresight-cti", "arm,primecell";
2677 clock-names = "apb_pclk";
2686 clock-names = "apb_pclk";
2688 arm,coresight-loses-context-with-cpu;
2689 qcom,skip-power-up;
2691 out-ports {
2694 remote-endpoint = <&funnel_apss_in7>;
2701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2705 clock-names = "apb_pclk";
2707 in-ports {
2708 #address-cells = <1>;
2709 #size-cells = <0>;
2715 remote-endpoint = <&etm0_out>;
2723 remote-endpoint = <&etm1_out>;
2731 remote-endpoint = <&etm2_out>;
2739 remote-endpoint = <&etm3_out>;
2747 remote-endpoint = <&etm4_out>;
2755 remote-endpoint = <&etm5_out>;
2763 remote-endpoint = <&etm6_out>;
2771 remote-endpoint = <&etm7_out>;
2776 out-ports {
2779 remote-endpoint = <&funnel_apss_merg_in0>;
2786 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2790 clock-names = "apb_pclk";
2792 in-ports {
2793 #address-cells = <1>;
2794 #size-cells = <0>;
2800 remote-endpoint = <&funnel_apss_out>;
2808 remote-endpoint = <&tpda_olc_out>;
2816 remote-endpoint = <&tpda_llm_silver_out>;
2824 remote-endpoint = <&tpda_llm_gold_out>;
2832 remote-endpoint = <&tpda_apss_out>;
2837 out-ports {
2840 remote-endpoint = <&funnel_in1_in7>;
2847 compatible = "qcom,coresight-tpdm", "arm,primecell";
2851 clock-names = "apb_pclk";
2853 qcom,cmb-element-bits = <64>;
2854 qcom,cmb-msrs-num = <32>;
2856 out-ports {
2859 remote-endpoint = <&tpda_olc_in>;
2866 compatible = "qcom,coresight-tpda", "arm,primecell";
2870 clock-names = "apb_pclk";
2872 in-ports {
2875 remote-endpoint = <&tpdm_olc_out>;
2880 out-ports {
2883 remote-endpoint = <&funnel_apss_merg_in2>;
2890 compatible = "qcom,coresight-tpdm", "arm,primecell";
2894 clock-names = "apb_pclk";
2896 qcom,dsb-element-bits = <32>;
2897 qcom,dsb-msrs-num = <32>;
2899 out-ports {
2902 remote-endpoint = <&tpda_apss_in>;
2909 compatible = "qcom,coresight-tpda", "arm,primecell";
2913 clock-names = "apb_pclk";
2915 in-ports {
2918 remote-endpoint = <&tpdm_apss_out>;
2923 out-ports {
2926 remote-endpoint = <&funnel_apss_merg_in5>;
2933 compatible = "qcom,coresight-tpdm", "arm,primecell";
2937 clock-names = "apb_pclk";
2939 qcom,cmb-element-bits = <32>;
2940 qcom,cmb-msrs-num = <32>;
2942 out-ports {
2945 remote-endpoint = <&tpda_llm_silver_in>;
2952 compatible = "qcom,coresight-tpdm", "arm,primecell";
2956 clock-names = "apb_pclk";
2958 qcom,cmb-element-bits = <32>;
2959 qcom,cmb-msrs-num = <32>;
2961 out-ports {
2964 remote-endpoint = <&tpda_llm_gold_in>;
2971 compatible = "qcom,coresight-tpda", "arm,primecell";
2975 clock-names = "apb_pclk";
2977 in-ports {
2980 remote-endpoint = <&tpdm_llm_silver_out>;
2985 out-ports {
2988 remote-endpoint = <&funnel_apss_merg_in3>;
2995 compatible = "qcom,coresight-tpda", "arm,primecell";
2999 clock-names = "apb_pclk";
3001 in-ports {
3004 remote-endpoint = <&tpdm_llm_gold_out>;
3009 out-ports {
3012 remote-endpoint = <&funnel_apss_merg_in4>;
3019 compatible = "arm,coresight-cti", "arm,primecell";
3023 clock-names = "apb_pclk";
3027 compatible = "arm,coresight-cti", "arm,primecell";
3031 clock-names = "apb_pclk";
3035 compatible = "arm,coresight-cti", "arm,primecell";
3039 clock-names = "apb_pclk";
3043 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon";
3049 operating-points-v2 = <&cpu_bwmon_opp_table>;
3051 cpu_bwmon_opp_table: opp-table {
3052 compatible = "operating-points-v2";
3054 opp-0 {
3055 opp-peak-kBps = <12896000>;
3058 opp-1 {
3059 opp-peak-kBps = <14928000>;
3065 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3071 operating-points-v2 = <&llcc_bwmon_opp_table>;
3073 llcc_bwmon_opp_table: opp-table {
3074 compatible = "operating-points-v2";
3076 opp-0 {
3077 opp-peak-kBps = <800000>;
3080 opp-1 {
3081 opp-peak-kBps = <1200000>;
3084 opp-2 {
3085 opp-peak-kBps = <1804800>;
3088 opp-3 {
3089 opp-peak-kBps = <2188800>;
3092 opp-4 {
3093 opp-peak-kBps = <2726400>;
3096 opp-5 {
3097 opp-peak-kBps = <3072000>;
3100 opp-6 {
3101 opp-peak-kBps = <4070400>;
3104 opp-7 {
3105 opp-peak-kBps = <5414400>;
3108 opp-8 {
3109 opp-peak-kBps = <6220800>;
3115 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
3117 reg-names = "hc";
3121 interrupt-names = "hc_irq",
3127 clock-names = "iface",
3131 power-domains = <&rpmhpd RPMHPD_CX>;
3132 operating-points-v2 = <&sdhc2_opp_table>;
3139 interconnect-names = "sdhc-ddr",
3140 "cpu-sdhc";
3142 qcom,dll-config = <0x0007642c>;
3143 qcom,ddr-config = <0x80040868>;
3144 dma-coherent;
3148 sdhc2_opp_table: opp-table {
3149 compatible = "operating-points-v2";
3151 opp-50000000 {
3152 opp-hz = /bits/ 64 <50000000>;
3153 required-opps = <&rpmhpd_opp_low_svs>;
3156 opp-100000000 {
3157 opp-hz = /bits/ 64 <100000000>;
3158 required-opps = <&rpmhpd_opp_svs>;
3161 opp-202000000 {
3162 opp-hz = /bits/ 64 <202000000>;
3163 required-opps = <&rpmhpd_opp_nom>;
3170 compatible = "qcom,qcs615-dc-noc";
3171 #interconnect-cells = <2>;
3172 qcom,bcm-voters = <&apps_bcm_voter>;
3175 llcc: system-cache-controller@9200000 {
3176 compatible = "qcom,qcs615-llcc";
3179 reg-names = "llcc0_base",
3185 compatible = "qcom,qcs615-gem-noc";
3186 #interconnect-cells = <2>;
3187 qcom,bcm-voters = <&apps_bcm_voter>;
3190 pdc: interrupt-controller@b220000 {
3191 compatible = "qcom,qcs615-pdc", "qcom,pdc";
3194 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3195 interrupt-parent = <&intc>;
3196 #interrupt-cells = <2>;
3197 interrupt-controller;
3200 aoss_qmp: power-controller@c300000 {
3201 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp";
3206 #clock-cells = <0>;
3207 #power-domain-cells = <1>;
3211 compatible = "qcom,rpmh-stats";
3216 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3218 #iommu-cells = <2>;
3219 #global-interrupts = <1>;
3220 dma-coherent;
3290 compatible = "qcom,spmi-pmic-arb";
3296 reg-names = "core",
3301 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3302 interrupt-names = "periph_irq";
3303 interrupt-controller;
3304 #interrupt-cells = <4>;
3305 #address-cells = <2>;
3306 #size-cells = <0>;
3307 cell-index = <0>;
3312 intc: interrupt-controller@17a00000 {
3313 compatible = "arm,gic-v3";
3317 #interrupt-cells = <3>;
3318 interrupt-controller;
3319 #redistributor-regions = <1>;
3320 redistributor-stride = <0x0 0x20000>;
3324 compatible = "qcom,qcs615-apss-shared",
3325 "qcom,sdm845-apss-shared";
3327 #mbox-cells = <1>;
3331 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
3337 compatible = "arm,armv7-timer-mem";
3340 #address-cells = <1>;
3341 #size-cells = <1>;
3346 frame-number = <0>;
3353 frame-number = <1>;
3360 frame-number = <2>;
3367 frame-number = <3>;
3374 frame-number = <4>;
3381 frame-number = <5>;
3388 frame-number = <6>;
3395 compatible = "qcom,rpmh-rsc";
3399 reg-names = "drv-0",
3400 "drv-1",
3401 "drv-2";
3407 qcom,drv-id = <2>;
3408 qcom,tcs-offset = <0xd00>;
3409 qcom,tcs-config = <ACTIVE_TCS 2>,
3415 power-domains = <&cluster_pd>;
3417 apps_bcm_voter: bcm-voter {
3418 compatible = "qcom,bcm-voter";
3421 rpmhcc: clock-controller {
3422 compatible = "qcom,qcs615-rpmh-clk";
3423 clock-names = "xo";
3425 #clock-cells = <1>;
3428 rpmhpd: power-controller {
3429 compatible = "qcom,qcs615-rpmhpd";
3430 #power-domain-cells = <1>;
3431 operating-points-v2 = <&rpmhpd_opp_table>;
3433 rpmhpd_opp_table: opp-table {
3434 compatible = "operating-points-v2";
3436 rpmhpd_opp_ret: opp-0 {
3437 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3440 rpmhpd_opp_min_svs: opp-1 {
3441 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3444 rpmhpd_opp_low_svs: opp-2 {
3445 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3448 rpmhpd_opp_svs: opp-3 {
3449 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3452 rpmhpd_opp_svs_l1: opp-4 {
3453 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3456 rpmhpd_opp_nom: opp-5 {
3457 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3460 rpmhpd_opp_nom_l1: opp-6 {
3461 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3464 rpmhpd_opp_nom_l2: opp-7 {
3465 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3468 rpmhpd_opp_turbo: opp-8 {
3469 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3472 rpmhpd_opp_turbo_l1: opp-9 {
3473 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3480 compatible = "qcom,qcs615-qusb2-phy";
3484 clock-names = "cfg_ahb", "ref";
3487 nvmem-cells = <&qusb2_hstx_trim>;
3489 #phy-cells = <0>;
3495 compatible = "qcom,qcs615-qusb2-phy";
3500 clock-names = "cfg_ahb",
3505 #phy-cells = <0>;
3511 compatible = "qcom,qcs615-qmp-usb3-phy";
3518 clock-names = "aux",
3525 reset-names = "phy", "phy_phy";
3527 qcom,tcsr-reg = <&tcsr 0xb244>;
3529 clock-output-names = "usb3_phy_pipe_clk_src";
3530 #clock-cells = <0>;
3532 #phy-cells = <0>;
3538 compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
3547 clock-names = "cfg_noc",
3554 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3556 assigned-clock-rates = <19200000>, <200000000>;
3558 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3563 interrupt-names = "pwr_event",
3569 power-domains = <&gcc USB30_PRIM_GDSC>;
3570 required-opps = <&rpmhpd_opp_nom>;
3574 #address-cells = <2>;
3575 #size-cells = <2>;
3588 phy-names = "usb2-phy", "usb3-phy";
3590 snps,dis-u1-entry-quirk;
3591 snps,dis-u2-entry-quirk;
3594 snps,has-lpm-erratum;
3595 snps,hird-threshold = /bits/ 8 <0x10>;
3601 compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
3610 clock-names = "cfg_noc",
3617 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
3619 assigned-clock-rates = <19200000>, <200000000>;
3621 interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
3625 interrupt-names = "pwr_event",
3630 power-domains = <&gcc USB20_SEC_GDSC>;
3631 required-opps = <&rpmhpd_opp_nom>;
3635 qcom,select-utmi-as-pipe-clk;
3637 #address-cells = <2>;
3638 #size-cells = <2>;
3651 phy-names = "usb2-phy";
3655 snps,has-lpm-erratum;
3656 snps,hird-threshold = /bits/ 8 <0x10>;
3658 maximum-speed = "high-speed";
3664 compatible = "arm,armv8-timer";