Lines Matching +full:interrupt +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/pinctrl/mt65xx.h>
7 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a73";
23 enable-method = "psci";
26 clock-names = "cpu", "intermediate";
27 operating-points-v2 = <&cluster0_opp>;
31 compatible = "arm,cortex-a73";
34 enable-method = "psci";
37 clock-names = "cpu", "intermediate";
38 operating-points-v2 = <&cluster0_opp>;
42 compatible = "arm,cortex-a73";
45 enable-method = "psci";
48 clock-names = "cpu", "intermediate";
49 operating-points-v2 = <&cluster0_opp>;
53 compatible = "arm,cortex-a73";
56 enable-method = "psci";
59 clock-names = "cpu", "intermediate";
60 operating-points-v2 = <&cluster0_opp>;
63 cluster0_opp: opp-table-0 {
64 compatible = "operating-points-v2";
65 opp-shared;
67 opp-800000000 {
68 opp-hz = /bits/ 64 <800000000>;
69 opp-microvolt = <850000>;
71 opp-1100000000 {
72 opp-hz = /bits/ 64 <1100000000>;
73 opp-microvolt = <850000>;
75 opp-1500000000 {
76 opp-hz = /bits/ 64 <1500000000>;
77 opp-microvolt = <850000>;
79 opp-1800000000 {
80 opp-hz = /bits/ 64 <1800000000>;
81 opp-microvolt = <900000>;
86 oscillator-40m {
87 compatible = "fixed-clock";
88 clock-frequency = <40000000>;
89 #clock-cells = <0>;
90 clock-output-names = "clkxtal";
94 compatible = "arm,cortex-a73-pmu";
95 interrupt-parent = <&gic>;
100 compatible = "arm,psci-0.2";
104 reserved-memory {
105 #address-cells = <2>;
106 #size-cells = <2>;
112 no-map;
117 compatible = "simple-bus";
119 #address-cells = <2>;
120 #size-cells = <2>;
122 gic: interrupt-controller@c000000 {
123 compatible = "arm,gic-v3";
129 interrupt-parent = <&gic>;
131 interrupt-controller;
132 #interrupt-cells = <3>;
135 infracfg: clock-controller@10001000 {
136 compatible = "mediatek,mt7988-infracfg", "syscon";
138 #clock-cells = <1>;
139 #reset-cells = <1>;
142 topckgen: clock-controller@1001b000 {
143 compatible = "mediatek,mt7988-topckgen", "syscon";
145 #clock-cells = <1>;
149 compatible = "mediatek,mt7988-wdt";
152 #reset-cells = <1>;
155 apmixedsys: clock-controller@1001e000 {
156 compatible = "mediatek,mt7988-apmixedsys";
158 #clock-cells = <1>;
162 compatible = "mediatek,mt7988-pinctrl";
170 reg-names = "gpio", "iocfg_tr",
173 gpio-controller;
174 #gpio-cells = <2>;
175 gpio-ranges = <&pio 0 0 84>;
176 interrupt-controller;
178 interrupt-parent = <&gic>;
179 #interrupt-cells = <2>;
181 pcie0_pins: pcie0-pins {
189 pcie1_pins: pcie1-pins {
197 pcie2_pins: pcie2-pins {
205 pcie3_pins: pcie3-pins {
215 compatible = "mediatek,mt7988-pwm";
227 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
229 #pwm-cells = <2>;
234 compatible = "mediatek,mt7988-mcusys", "syscon";
236 #clock-cells = <1>;
240 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
243 interrupt-names = "uart", "wakeup";
246 clock-names = "baud", "bus";
251 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
254 interrupt-names = "uart", "wakeup";
257 clock-names = "baud", "bus";
262 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
265 interrupt-names = "uart", "wakeup";
268 clock-names = "baud", "bus";
273 compatible = "mediatek,mt7981-i2c";
277 clock-div = <1>;
280 clock-names = "main", "dma";
281 #address-cells = <1>;
282 #size-cells = <0>;
287 compatible = "mediatek,mt7981-i2c";
291 clock-div = <1>;
294 clock-names = "main", "dma";
295 #address-cells = <1>;
296 #size-cells = <0>;
301 compatible = "mediatek,mt7981-i2c";
305 clock-div = <1>;
308 clock-names = "main", "dma";
309 #address-cells = <1>;
310 #size-cells = <0>;
315 compatible = "mediatek,mt7988-lvts-ap";
316 #thermal-sensor-cells = <1>;
321 nvmem-cells = <&lvts_calibration>;
322 nvmem-cell-names = "lvts-calib-data-1";
326 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
329 reg-names = "mac", "ippc";
336 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
341 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
344 reg-names = "mac", "ippc";
351 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
358 compatible = "mediatek,mt7988-mmc";
366 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
368 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
370 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
371 #address-cells = <1>;
372 #size-cells = <0>;
377 compatible = "mediatek,mt7986-pcie",
378 "mediatek,mt8192-pcie";
380 #address-cells = <3>;
381 #size-cells = <2>;
383 reg-names = "pcie-mac";
384 linux,pci-domain = <3>;
386 bus-range = <0x00 0xff>;
395 clock-names = "pl_250m", "tl_26m", "peri_26m",
397 pinctrl-names = "default";
398 pinctrl-0 = <&pcie2_pins>;
401 #interrupt-cells = <1>;
402 interrupt-map-mask = <0 0 0 0x7>;
403 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
407 pcie_intc2: interrupt-controller {
408 #address-cells = <0>;
409 #interrupt-cells = <1>;
410 interrupt-controller;
415 compatible = "mediatek,mt7986-pcie",
416 "mediatek,mt8192-pcie";
418 #address-cells = <3>;
419 #size-cells = <2>;
421 reg-names = "pcie-mac";
422 linux,pci-domain = <2>;
424 bus-range = <0x00 0xff>;
433 clock-names = "pl_250m", "tl_26m", "peri_26m",
435 pinctrl-names = "default";
436 pinctrl-0 = <&pcie3_pins>;
439 #interrupt-cells = <1>;
440 interrupt-map-mask = <0 0 0 0x7>;
441 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
445 pcie_intc3: interrupt-controller {
446 #address-cells = <0>;
447 #interrupt-cells = <1>;
448 interrupt-controller;
453 compatible = "mediatek,mt7986-pcie",
454 "mediatek,mt8192-pcie";
456 #address-cells = <3>;
457 #size-cells = <2>;
459 reg-names = "pcie-mac";
460 linux,pci-domain = <0>;
462 bus-range = <0x00 0xff>;
471 clock-names = "pl_250m", "tl_26m", "peri_26m",
473 pinctrl-names = "default";
474 pinctrl-0 = <&pcie0_pins>;
477 #interrupt-cells = <1>;
478 interrupt-map-mask = <0 0 0 0x7>;
479 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
483 pcie_intc0: interrupt-controller {
484 #address-cells = <0>;
485 #interrupt-cells = <1>;
486 interrupt-controller;
491 compatible = "mediatek,mt7986-pcie",
492 "mediatek,mt8192-pcie";
494 #address-cells = <3>;
495 #size-cells = <2>;
497 reg-names = "pcie-mac";
498 linux,pci-domain = <1>;
500 bus-range = <0x00 0xff>;
509 clock-names = "pl_250m", "tl_26m", "peri_26m",
511 pinctrl-names = "default";
512 pinctrl-0 = <&pcie1_pins>;
515 #interrupt-cells = <1>;
516 interrupt-map-mask = <0 0 0 0x7>;
517 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
521 pcie_intc1: interrupt-controller {
522 #address-cells = <0>;
523 #interrupt-cells = <1>;
524 interrupt-controller;
528 tphy: t-phy@11c50000 {
529 compatible = "mediatek,mt7986-tphy",
530 "mediatek,generic-tphy-v2";
531 #address-cells = <2>;
532 #size-cells = <2>;
536 tphyu2port0: usb-phy@11c50000 {
539 clock-names = "ref";
540 #phy-cells = <1>;
543 tphyu3port0: usb-phy@11c50700 {
546 clock-names = "ref";
547 #phy-cells = <1>;
551 clock-controller@11f40000 {
552 compatible = "mediatek,mt7988-xfi-pll";
555 #clock-cells = <1>;
559 compatible = "mediatek,mt7988-efuse", "mediatek,efuse";
561 #address-cells = <1>;
562 #size-cells = <1>;
569 clock-controller@15000000 {
570 compatible = "mediatek,mt7988-ethsys", "syscon";
572 #clock-cells = <1>;
573 #reset-cells = <1>;
576 clock-controller@15031000 {
577 compatible = "mediatek,mt7988-ethwarp";
579 #clock-cells = <1>;
580 #reset-cells = <1>;
584 thermal-zones {
585 cpu_thermal: cpu-thermal {
586 polling-delay-passive = <1000>;
587 polling-delay = <1000>;
588 thermal-sensors = <&lvts 0>;
600 compatible = "arm,armv8-timer";
601 interrupt-parent = <&gic>;