Lines Matching full:clocks
82 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
94 clocks: clock-controller@e0100000 { label
98 clocks = <&xxti>, <&xusbxti>;
125 clocks = <&clocks CLK_PDMA0>;
135 clocks = <&clocks CLK_PDMA1>;
145 clocks = <&clocks CLK_TSADC>;
158 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
175 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
190 clocks = <&clocks CLK_KEYIF>;
200 clocks = <&clocks CLK_I2C0>;
214 clocks = <&clocks CLK_I2C2>;
229 clocks = <&clocks DOUT_HCLKP>, <&xxti>,
230 <&clocks FOUT_EPLL>,
231 <&clocks SCLK_AUDIO0>;
245 clocks = <&clk_audss CLK_I2S>,
263 clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>;
278 clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>;
291 clocks = <&clocks CLK_PWM>;
301 clocks = <&clocks CLK_WDT>;
309 clocks = <&clocks CLK_RTC>;
321 clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
322 <&clocks SCLK_UART0>;
333 clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>,
334 <&clocks SCLK_UART1>;
345 clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>,
346 <&clocks SCLK_UART2>;
357 clocks = <&clocks CLK_UART3>, <&clocks CLK_UART3>,
358 <&clocks SCLK_UART3>;
368 clocks = <&clocks CLK_HSMMC0>, <&clocks CLK_HSMMC0>,
369 <&clocks SCLK_MMC0>;
379 clocks = <&clocks CLK_HSMMC1>, <&clocks CLK_HSMMC1>,
380 <&clocks SCLK_MMC1>;
390 clocks = <&clocks CLK_HSMMC2>, <&clocks CLK_HSMMC2>,
391 <&clocks SCLK_MMC2>;
401 clocks = <&clocks CLK_HSMMC3>, <&clocks CLK_HSMMC3>,
402 <&clocks SCLK_MMC3>;
411 clocks = <&clocks CLK_USB_OTG>;
422 clocks = <&clocks CLK_USB_OTG>, <&xusbxti>;
433 clocks = <&clocks CLK_USB_HOST>;
445 clocks = <&clocks CLK_USB_HOST>;
457 clocks = <&clocks CLK_MFC>, <&clocks DOUT_MFC>;
495 clocks = <&clocks SCLK_FIMD>, <&clocks CLK_FIMD>;
515 clocks = <&clocks DOUT_G2D>, <&clocks CLK_G2D>;
524 clocks = <&clocks CLK_MDMA>;
534 clocks = <&clocks CLK_ROTATOR>;
543 clocks = <&clocks CLK_I2C1>;
555 clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>;
567 clocks = <&clocks CLK_CSIS>,
568 <&clocks SCLK_CSIS>;
582 clocks = <&clocks CLK_FIMC0>,
583 <&clocks SCLK_FIMC0>;
596 clocks = <&clocks CLK_FIMC1>,
597 <&clocks SCLK_FIMC1>;
612 clocks = <&clocks CLK_FIMC2>,
613 <&clocks SCLK_FIMC2>;
628 clocks = <&clocks CLK_JPEG>;