Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 interrupt-parent = <&gic>;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a7";
41 reg = <0xf00>;
42 enable-method = "psci";
48 compatible = "arm,cortex-a7";
49 reg = <0xf01>;
50 enable-method = "psci";
56 compatible = "arm,cortex-a7";
57 reg = <0xf02>;
58 enable-method = "psci";
64 compatible = "arm,cortex-a7";
65 reg = <0xf03>;
66 enable-method = "psci";
71 arm-pmu {
72 compatible = "arm,cortex-a7-pmu";
77 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
81 compatible = "arm,psci-1.0";
86 compatible = "arm,armv7-timer";
91 clock-frequency = <24000000>;
95 compatible = "rockchip,display-subsystem";
100 compatible = "fixed-clock";
101 clock-frequency = <24000000>;
102 clock-output-names = "xin24m";
103 #clock-cells = <0>;
107 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
108 reg = <0xfe000000 0x20000>;
112 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
113 reg = <0xfe020000 0x1000>;
115 pmu_io_domains: io-domains {
116 compatible = "rockchip,rv1126-pmu-io-voltage-domain";
122 compatible = "rockchip,rv1126-qos", "syscon";
123 reg = <0xfe860000 0x20>;
127 compatible = "rockchip,rv1126-qos", "syscon";
128 reg = <0xfe860080 0x20>;
132 compatible = "rockchip,rv1126-qos", "syscon";
133 reg = <0xfe860200 0x20>;
137 compatible = "rockchip,rv1126-qos", "syscon";
138 reg = <0xfe86c000 0x20>;
142 compatible = "rockchip,rv1126-qos", "syscon";
143 reg = <0xfe8a0000 0x20>;
147 compatible = "rockchip,rv1126-qos", "syscon";
148 reg = <0xfe8a0080 0x20>;
152 compatible = "rockchip,rv1126-qos", "syscon";
153 reg = <0xfe8a0100 0x20>;
157 compatible = "rockchip,rv1126-qos", "syscon";
158 reg = <0xfe8a0180 0x20>;
161 gic: interrupt-controller@feff0000 {
162 compatible = "arm,gic-400";
163 interrupt-controller;
164 #interrupt-cells = <3>;
165 #address-cells = <0>;
167 reg = <0xfeff1000 0x1000>,
174 pmu: power-management@ff3e0000 {
175 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
176 reg = <0xff3e0000 0x1000>;
178 power: power-controller {
179 compatible = "rockchip,rv1126-power-controller";
180 #power-domain-cells = <1>;
181 #address-cells = <1>;
182 #size-cells = <0>;
184 power-domain@RV1126_PD_NVM {
185 reg = <RV1126_PD_NVM>;
196 #power-domain-cells = <0>;
199 power-domain@RV1126_PD_SDIO {
200 reg = <RV1126_PD_SDIO>;
204 #power-domain-cells = <0>;
207 power-domain@RV1126_PD_VO {
208 reg = <RV1126_PD_VO>;
223 #power-domain-cells = <0>;
229 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
230 reg = <0xff3f0000 0x1000>;
234 clock-names = "i2c", "pclk";
235 pinctrl-names = "default";
236 pinctrl-0 = <&i2c0_xfer>;
237 #address-cells = <1>;
238 #size-cells = <0>;
243 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
244 reg = <0xff400000 0x1000>;
248 clock-names = "i2c", "pclk";
249 pinctrl-names = "default";
250 pinctrl-0 = <&i2c2_xfer>;
251 #address-cells = <1>;
252 #size-cells = <0>;
257 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
258 reg = <0xff410000 0x100>;
260 clock-frequency = <24000000>;
262 clock-names = "baudclk", "apb_pclk";
264 dma-names = "tx", "rx";
265 pinctrl-names = "default";
266 pinctrl-0 = <&uart1m0_xfer>;
267 reg-shift = <2>;
268 reg-io-width = <4>;
273 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
274 reg = <0xff430000 0x10>;
275 clock-names = "pwm", "pclk";
277 pinctrl-names = "default";
278 pinctrl-0 = <&pwm0m0_pins>;
279 #pwm-cells = <3>;
284 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
285 reg = <0xff430010 0x10>;
286 clock-names = "pwm", "pclk";
288 pinctrl-names = "default";
289 pinctrl-0 = <&pwm1m0_pins>;
290 #pwm-cells = <3>;
295 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
296 reg = <0xff430020 0x10>;
297 clock-names = "pwm", "pclk";
299 pinctrl-names = "default";
300 pinctrl-0 = <&pwm2m0_pins>;
301 #pwm-cells = <3>;
306 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
307 reg = <0xff430030 0x10>;
308 clock-names = "pwm", "pclk";
310 pinctrl-names = "default";
311 pinctrl-0 = <&pwm3m0_pins>;
312 #pwm-cells = <3>;
317 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
318 reg = <0xff440000 0x10>;
319 clock-names = "pwm", "pclk";
321 pinctrl-names = "default";
322 pinctrl-0 = <&pwm4m0_pins>;
323 #pwm-cells = <3>;
328 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
329 reg = <0xff440010 0x10>;
330 clock-names = "pwm", "pclk";
332 pinctrl-names = "default";
333 pinctrl-0 = <&pwm5m0_pins>;
334 #pwm-cells = <3>;
339 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
340 reg = <0xff440020 0x10>;
341 clock-names = "pwm", "pclk";
343 pinctrl-names = "default";
344 pinctrl-0 = <&pwm6m0_pins>;
345 #pwm-cells = <3>;
350 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
351 reg = <0xff440030 0x10>;
352 clock-names = "pwm", "pclk";
354 pinctrl-names = "default";
355 pinctrl-0 = <&pwm7m0_pins>;
356 #pwm-cells = <3>;
360 pmucru: clock-controller@ff480000 {
361 compatible = "rockchip,rv1126-pmucru";
362 reg = <0xff480000 0x1000>;
364 #clock-cells = <1>;
365 #reset-cells = <1>;
368 cru: clock-controller@ff490000 {
369 compatible = "rockchip,rv1126-cru";
370 reg = <0xff490000 0x1000>;
372 clock-names = "xin24m";
374 #clock-cells = <1>;
375 #reset-cells = <1>;
378 dmac: dma-controller@ff4e0000 {
380 reg = <0xff4e0000 0x4000>;
383 #dma-cells = <1>;
384 arm,pl330-periph-burst;
386 clock-names = "apb_pclk";
390 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
391 reg = <0xff520000 0x1000>;
394 clock-names = "i2c", "pclk";
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c3m0_xfer>;
398 #address-cells = <1>;
399 #size-cells = <0>;
404 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
405 reg = <0xff550000 0x10>;
406 clock-names = "pwm", "pclk";
408 pinctrl-0 = <&pwm8m0_pins>;
409 pinctrl-names = "default";
410 #pwm-cells = <3>;
415 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
416 reg = <0xff550010 0x10>;
417 clock-names = "pwm", "pclk";
419 pinctrl-0 = <&pwm9m0_pins>;
420 pinctrl-names = "default";
421 #pwm-cells = <3>;
426 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
427 reg = <0xff550020 0x10>;
428 clock-names = "pwm", "pclk";
430 pinctrl-0 = <&pwm10m0_pins>;
431 pinctrl-names = "default";
432 #pwm-cells = <3>;
437 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
438 reg = <0xff550030 0x10>;
439 clock-names = "pwm", "pclk";
441 pinctrl-0 = <&pwm11m0_pins>;
442 pinctrl-names = "default";
443 #pwm-cells = <3>;
448 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
449 reg = <0xff560000 0x100>;
451 clock-frequency = <24000000>;
453 clock-names = "baudclk", "apb_pclk";
455 dma-names = "tx", "rx";
456 pinctrl-names = "default";
457 pinctrl-0 = <&uart0_xfer>;
458 reg-shift = <2>;
459 reg-io-width = <4>;
464 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
465 reg = <0xff570000 0x100>;
467 clock-frequency = <24000000>;
469 clock-names = "baudclk", "apb_pclk";
471 dma-names = "tx", "rx";
472 pinctrl-names = "default";
473 pinctrl-0 = <&uart2m1_xfer>;
474 reg-shift = <2>;
475 reg-io-width = <4>;
480 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
481 reg = <0xff580000 0x100>;
483 clock-frequency = <24000000>;
485 clock-names = "baudclk", "apb_pclk";
487 dma-names = "tx", "rx";
488 pinctrl-names = "default";
489 pinctrl-0 = <&uart3m0_xfer>;
490 reg-shift = <2>;
491 reg-io-width = <4>;
496 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
497 reg = <0xff590000 0x100>;
499 clock-frequency = <24000000>;
501 clock-names = "baudclk", "apb_pclk";
503 dma-names = "tx", "rx";
504 pinctrl-names = "default";
505 pinctrl-0 = <&uart4m0_xfer>;
506 reg-shift = <2>;
507 reg-io-width = <4>;
512 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
513 reg = <0xff5a0000 0x100>;
515 clock-frequency = <24000000>;
517 clock-names = "baudclk", "apb_pclk";
519 dma-names = "tx", "rx";
520 pinctrl-names = "default";
521 pinctrl-0 = <&uart5m0_xfer>;
522 reg-shift = <2>;
523 reg-io-width = <4>;
528 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
529 reg = <0xff5e0000 0x100>;
531 #io-channel-cells = <1>;
533 clock-names = "saradc", "apb_pclk";
535 reset-names = "saradc-apb";
540 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
541 reg = <0xff660000 0x20>;
544 clock-names = "pclk", "timer";
548 compatible = "rockchip,rv1126-wdt", "snps,dw-wdt";
549 reg = <0xff680000 0x100>;
556 compatible = "rockchip,rv1126-i2s-tdm";
557 reg = <0xff800000 0x1000>;
560 clock-names = "mclk_tx", "mclk_rx", "hclk";
562 dma-names = "tx", "rx";
563 pinctrl-names = "default";
564 pinctrl-0 = <&i2s0m0_sclk_tx>,
575 reset-names = "tx-m", "rx-m";
577 #sound-dai-cells = <0>;
582 compatible = "rockchip,rv1126-vop";
583 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
585 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
587 reset-names = "axi", "ahb", "dclk";
590 power-domains = <&power RV1126_PD_VO>;
594 #address-cells = <1>;
595 #size-cells = <0>;
598 reg = <0>;
602 reg = <1>;
609 reg = <0xffb00f00 0x100>;
611 clock-names = "aclk", "iface";
613 #iommu-cells = <0>;
614 power-domains = <&power RV1126_PD_VO>;
619 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
620 reg = <0xffc40000 0x4000>;
623 interrupt-names = "macirq", "eth_wake_irq";
629 clock-names = "stmmaceth", "mac_clk_rx",
634 reset-names = "stmmaceth";
636 snps,mixed-burst;
639 snps,axi-config = <&stmmac_axi_setup>;
640 snps,mtl-rx-config = <&mtl_rx_setup>;
641 snps,mtl-tx-config = <&mtl_tx_setup>;
645 compatible = "snps,dwmac-mdio";
646 #address-cells = <0x1>;
647 #size-cells = <0x0>;
650 stmmac_axi_setup: stmmac-axi-config {
656 mtl_rx_setup: rx-queues-config {
657 snps,rx-queues-to-use = <1>;
661 mtl_tx_setup: tx-queues-config {
662 snps,tx-queues-to-use = <1>;
668 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
669 reg = <0xffc50000 0x4000>;
673 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
674 fifo-depth = <0x100>;
675 max-frequency = <200000000>;
676 power-domains = <&power RV1126_PD_NVM>;
681 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
682 reg = <0xffc60000 0x4000>;
686 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
687 fifo-depth = <0x100>;
688 max-frequency = <200000000>;
693 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
694 reg = <0xffc70000 0x4000>;
698 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
699 fifo-depth = <0x100>;
700 max-frequency = <200000000>;
701 power-domains = <&power RV1126_PD_SDIO>;
707 reg = <0xffc90000 0x4000>;
709 assigned-clocks = <&cru SCLK_SFC>;
710 assigned-clock-rates = <80000000>;
711 clock-names = "clk_sfc", "hclk_sfc";
713 power-domains = <&power RV1126_PD_NVM>;
718 compatible = "rockchip,rv1126-pinctrl";
721 #address-cells = <1>;
722 #size-cells = <1>;
726 compatible = "rockchip,gpio-bank";
727 reg = <0xff460000 0x100>;
730 gpio-controller;
731 #gpio-cells = <2>;
732 interrupt-controller;
733 #interrupt-cells = <2>;
737 compatible = "rockchip,gpio-bank";
738 reg = <0xff620000 0x100>;
741 gpio-controller;
742 #gpio-cells = <2>;
743 interrupt-controller;
744 #interrupt-cells = <2>;
748 compatible = "rockchip,gpio-bank";
749 reg = <0xff630000 0x100>;
752 gpio-controller;
753 #gpio-cells = <2>;
754 interrupt-controller;
755 #interrupt-cells = <2>;
759 compatible = "rockchip,gpio-bank";
760 reg = <0xff640000 0x100>;
763 gpio-controller;
764 #gpio-cells = <2>;
765 interrupt-controller;
766 #interrupt-cells = <2>;
770 compatible = "rockchip,gpio-bank";
771 reg = <0xff650000 0x100>;
774 gpio-controller;
775 #gpio-cells = <2>;
776 interrupt-controller;
777 #interrupt-cells = <2>;
782 #include "rv1126-pinctrl.dtsi"