Lines Matching +full:0 +full:x10
72 pwms = <&pwm2 0 50000 0>;
73 brightness-levels = <0 4 8 16 32 64 128 248>;
81 pinctrl-0 = <&pinctrl_i2c3>;
86 reg = <0x24>;
97 reg = <0x38>;
108 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
109 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
110 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
111 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
112 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
113 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
114 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
115 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
116 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
117 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
118 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
119 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
125 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
126 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
132 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
133 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
134 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
135 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
136 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10
137 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
138 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
139 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
140 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
141 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
142 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
143 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
144 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
145 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
146 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
147 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
148 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
149 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
150 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
151 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
152 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
153 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
154 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
155 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
156 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
157 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
158 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
159 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
160 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
166 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
167 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
168 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
169 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
175 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x17059
181 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
182 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
183 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
184 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
185 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
186 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
192 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
193 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
194 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
195 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
196 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
197 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
205 lvds-channel@0 {
236 pinctrl-0 = <&pinctrl_uart3>;
243 pinctrl-0 = <&pinctrl_usdhc2>;