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13 Intel Chipsets such as Tiger Lake, Jasper Lake, Alder Lake, Raptor Lake and
14 Meteor Lake. IPU6 consists of two major systems: Input System (ISYS) and
28 store and load frame pixel streams and any other metadata.
31 interrupt handling, firmware authentication and global timer sync.
33 ISYS and PSYS Power flow
36 IPU6 driver initialize the ISYS and PSYS power up or down request by setting the
37 Buttress frequency control register for ISYS and PSYS
38 (``IPU6_BUTTRESS_REG_IS_FREQ_CTL`` and ``IPU6_BUTTRESS_REG_PS_FREQ_CTL``) in
56 clears the irq status and then calls specific ISYS or PSYS irq handler.
60 Security and firmware authentication
70 registers used by the CSE and the IPU6 driver to communicate with each other via
86 DMA and MMU
89 The IPU6 has its own scalar processor where the firmware run at and an internal
91 allow that scalar processors to access the internal memory and external system
95 register and allows MMU to perform page table lookups.
98 page table entries for each DMA operation and invalidate the MMU TLB after each
99 unmap and free.
105 firmware contains a CPD header, several CPD entries and components. The CPD
106 component includes 3 entries - manifest, metadata and module data. Manifest and
107 metadata are defined by CSE and used by CSE for authentication. Module data is
109 directory. The IPU6 driver (``ipu6-cpd.c`` in particular) parses and validates
110 the CPD firmware file and gets the package directory binary data of the IPU6
111 firmware, copies it to specific DMA buffer and sets its base address to Buttress
120 inter-processor communication mechanism between the IPU scalar processors and
121 the CPU. There are a number of resources shared between firmware and software.
125 registers where the queue read and write indices reside. Software and firmware
126 function as producer and consumer of tokens in the queues and update the write
127 and read indices separately when sending or receiving each message.
129 The IPU6 driver must prepare and configure the number of input and output
130 queues, configure the count of tokens per queue and the size of per token before
131 initiating and starting the communication with firmware. Firmware and software
133 parameter registers which can be used to store the address of configuration and
134 initialise the Syscom state, then driver can request firmware to start and run via
140 IPU6 input system consists of MIPI D-PHY and several CSI-2 receivers.  It can
143 D-PHYs and CSI-2 ports lane mapping
146 The IPU6 integrates different D-PHY IPs on different SoCs, on Tiger Lake and
148 D-PHY and IPU6EP on Meteor Lake integrates a Synopsys DWC D-PHY. There is an
149 adaptional layer between D-PHY and CSI-2 receiver controller which includes port
151 D-PHY drivers ``ipu6-isys-mcd-phy.c``, ``ipu6-isys-jsl-phy.c`` and
155 there are 12 data lanes and 8 clock lanes, IPU6 support maximum 8 CSI-2 ports,
157 Lake and Alder Lake, D-PHY has 8 data lanes and 4 clock lanes, the IPU6 supports
158 maximum 4 CSI-2 ports. For Meteor Lake, D-PHY has 12 data lanes and 6 clock
162 	  lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support
167 	  and 1. The same applies to CSI ports 2/3, 4/5 and 7/8.
174 ipu6_fw_isys_stream_cfg_data_abi`` and sends the configuration to firmware via
175 sending ``STREAM_OPEN`` command. Stream configuration includes input pins and
177 resolution and data type of input source, output pin ``struct
178 ipu6_fw_isys_output_pin_info_abi`` defines the output resolution, stride and
182 successfully, the driver will send the ``STREAM_START`` and ``STREAM_CAPTURE``
185 ipu6_fw_isys_frame_buff_set``, software then waits for the interrupt and
187 output pin and then software can return the buffer to user.