Lines Matching +full:pdc +full:- +full:ranges
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <[email protected]>
14 controller with wrapping arbitration logic to allow for multiple on-chip
23 - items:
24 - const: qcom,sar2130p-spmi-pmic-arb
25 - const: qcom,x1e80100-spmi-pmic-arb
26 - const: qcom,x1e80100-spmi-pmic-arb
30 - description: core registers
31 - description: tx-channel per virtual slave registers
32 - description: rx-channel (called observer) per virtual slave registers
34 reg-names:
36 - const: core
37 - const: chnls
38 - const: obsrvr
40 ranges: true
42 '#address-cells':
45 '#size-cells':
63 "^spmi@[a-f0-9]+$":
71 - description: configuration registers
72 - description: interrupt controller registers
74 reg-names:
76 - const: cnfg
77 - const: intr
82 interrupt-names:
85 interrupt-controller: true
87 '#interrupt-cells':
90 cell 1: slave ID for the requested interrupt (0-15)
91 cell 2: peripheral ID for requested interrupt (0-255)
92 cell 3: the requested peripheral interrupt (0-7)
93 cell 4: interrupt flags indicating level-sense information,
94 as defined in dt-bindings/interrupt-controller/irq.h
97 - compatible
98 - reg-names
99 - qcom,ee
100 - qcom,channel
105 - |
106 #include <dt-bindings/interrupt-controller/arm-gic.h>
109 #address-cells = <2>;
110 #size-cells = <2>;
113 compatible = "qcom,x1e80100-spmi-pmic-arb";
117 reg-names = "core", "chnls", "obsrvr";
122 #address-cells = <2>;
123 #size-cells = <2>;
124 ranges;
129 reg-names = "cnfg", "intr";
131 interrupt-names = "periph_irq";
132 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
133 interrupt-controller;
134 #interrupt-cells = <4>;
136 #address-cells = <2>;
137 #size-cells = <0>;