Lines Matching full:mpc5200
1 MPC5200 Device Tree Bindings
9 For mpc5200 on-chip devices, the format for each compatible value is
15 The split between the MPC5200 and the MPC5200B leaves a bit of a
18 chip? For the MPC5200; the answer is easy. Most of the SoC devices
19 originally appeared on the MPC5200. Since they didn't exist anywhere
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
32 (instead of only listing the base mpc5200 item).
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
41 function. For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe
42 the mpc5200 simple spi device and a PSC spi mode respectively.
44 At the time of writing, exact chip may be either 'fsl,mpc5200' or
49 This node describes the on chip SOC peripherals. Every mpc5200 based
59 compatible mpc5200: "fsl,mpc5200-immr"
70 Note: The tables below show the value for the mpc5200. A mpc5200b device
71 tree should use the "fsl,mpc5200b-<device>","fsl,mpc5200-<device>" form.
76 cdm@<addr> fsl,mpc5200-cdm Clock Distribution
77 interrupt-controller@<addr> fsl,mpc5200-pic need an interrupt
79 bestcomm@<addr> fsl,mpc5200-bestcomm Bestcomm DMA controller
84 timer@<addr> fsl,mpc5200-gpt General purpose timers
85 gpio@<addr> fsl,mpc5200-gpio MPC5200 simple gpio controller
86 gpio@<addr> fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio controller
87 rtc@<addr> fsl,mpc5200-rtc Real time clock
88 mscan@<addr> fsl,mpc5200-mscan CAN bus controller
89 pci@<addr> fsl,mpc5200-pci PCI bridge
90 serial@<addr> fsl,mpc5200-psc-uart PSC in serial mode
91 i2s@<addr> fsl,mpc5200-psc-i2s PSC in i2s mode
92 ac97@<addr> fsl,mpc5200-psc-ac97 PSC in ac97 mode
93 spi@<addr> fsl,mpc5200-psc-spi PSC in spi mode
94 irda@<addr> fsl,mpc5200-psc-irda PSC in IrDA mode
95 spi@<addr> fsl,mpc5200-spi MPC5200 spi device
96 ethernet@<addr> fsl,mpc5200-fec MPC5200 ethernet device
97 ata@<addr> fsl,mpc5200-ata IDE ATA interface
98 i2c@<addr> fsl,mpc5200-i2c I2C controller
99 usb@<addr> fsl,mpc5200-ohci,ohci-be USB controller
100 xlb@<addr> fsl,mpc5200-xlb XLB arbitrator
102 fsl,mpc5200-gpt nodes
104 On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board
123 An mpc5200-gpt can be used as a single line GPIO controller. To do so,
131 An mpc5200-gpt can be used as a single line edge sensitive interrupt
138 fsl,mpc5200-psc nodes
146 PSC in i2s mode: The mpc5200 and mpc5200b PSCs are not compatible when in
147 i2s mode. An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the
151 fsl,mpc5200-gpio and fsl,mpc5200-gpio-wkup nodes
158 fsl,mpc5200-fec nodes
170 Interrupt controller (fsl,mpc5200-pic) node
172 The mpc5200 pic binding splits hardware IRQ numbers into two levels. The
179 The interrupts property for device nodes using the mpc5200 pic consists
196 fsl,mpc5200-mscan nodes
198 See file Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt