Lines Matching +full:phy +full:- +full:names
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <[email protected]>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,qcs615-qmp-gen3x1-pcie-phy
20 - qcom,sa8775p-qmp-gen4x2-pcie-phy
21 - qcom,sa8775p-qmp-gen4x4-pcie-phy
22 - qcom,sar2130p-qmp-gen3x2-pcie-phy
23 - qcom,sc8180x-qmp-pcie-phy
24 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
25 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
26 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
27 - qcom,sdm845-qhp-pcie-phy
28 - qcom,sdm845-qmp-pcie-phy
29 - qcom,sdx55-qmp-pcie-phy
30 - qcom,sdx65-qmp-gen4x2-pcie-phy
31 - qcom,sm8150-qmp-gen3x1-pcie-phy
32 - qcom,sm8150-qmp-gen3x2-pcie-phy
33 - qcom,sm8250-qmp-gen3x1-pcie-phy
34 - qcom,sm8250-qmp-gen3x2-pcie-phy
35 - qcom,sm8250-qmp-modem-pcie-phy
36 - qcom,sm8350-qmp-gen3x1-pcie-phy
37 - qcom,sm8350-qmp-gen3x2-pcie-phy
38 - qcom,sm8450-qmp-gen3x1-pcie-phy
39 - qcom,sm8450-qmp-gen4x2-pcie-phy
40 - qcom,sm8550-qmp-gen3x2-pcie-phy
41 - qcom,sm8550-qmp-gen4x2-pcie-phy
42 - qcom,sm8650-qmp-gen3x2-pcie-phy
43 - qcom,sm8650-qmp-gen4x2-pcie-phy
44 - qcom,x1e80100-qmp-gen3x2-pcie-phy
45 - qcom,x1e80100-qmp-gen4x2-pcie-phy
46 - qcom,x1e80100-qmp-gen4x4-pcie-phy
47 - qcom,x1e80100-qmp-gen4x8-pcie-phy
57 clock-names:
60 - const: aux
61 - const: cfg_ahb
62 - const: ref
63 - enum: [rchng, refgen]
64 - const: pipe
65 - const: pipediv2
66 - const: phy_aux
68 power-domains:
75 reset-names:
78 - const: phy
79 - const: phy_nocsr
81 vdda-phy-supply: true
83 vdda-pll-supply: true
85 vdda-qref-supply: true
87 qcom,4ln-config-sel:
88 description: PCIe 4-lane configuration
89 $ref: /schemas/types.yaml#/definitions/phandle-array
91 - items:
92 - description: phandle of TCSR syscon
93 - description: offset of PCIe 4-lane configuration register
94 - description: offset of configuration bit for this PHY
96 "#clock-cells": true
98 clock-output-names:
101 "#phy-cells":
105 - compatible
106 - reg
107 - clocks
108 - clock-names
109 - resets
110 - reset-names
111 - vdda-phy-supply
112 - vdda-pll-supply
113 - "#clock-cells"
114 - clock-output-names
115 - "#phy-cells"
120 - if:
125 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
126 - qcom,x1e80100-qmp-gen4x4-pcie-phy
131 - description: port a
132 - description: port b
134 - qcom,4ln-config-sel
140 - if:
145 - qcom,sar2130p-qmp-gen3x2-pcie-phy
146 - qcom,sc8180x-qmp-pcie-phy
147 - qcom,sdm845-qhp-pcie-phy
148 - qcom,sdm845-qmp-pcie-phy
149 - qcom,sdx55-qmp-pcie-phy
150 - qcom,sm8150-qmp-gen3x1-pcie-phy
151 - qcom,sm8150-qmp-gen3x2-pcie-phy
152 - qcom,sm8250-qmp-gen3x1-pcie-phy
153 - qcom,sm8250-qmp-gen3x2-pcie-phy
154 - qcom,sm8250-qmp-modem-pcie-phy
155 - qcom,sm8350-qmp-gen3x1-pcie-phy
156 - qcom,sm8350-qmp-gen3x2-pcie-phy
157 - qcom,sm8450-qmp-gen3x1-pcie-phy
158 - qcom,sm8450-qmp-gen3x2-pcie-phy
159 - qcom,sm8550-qmp-gen3x2-pcie-phy
160 - qcom,sm8550-qmp-gen4x2-pcie-phy
161 - qcom,sm8650-qmp-gen3x2-pcie-phy
162 - qcom,sm8650-qmp-gen4x2-pcie-phy
167 clock-names:
170 - if:
175 - qcom,qcs615-qmp-gen3x1-pcie-phy
176 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
177 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
178 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
179 - qcom,x1e80100-qmp-gen3x2-pcie-phy
180 - qcom,x1e80100-qmp-gen4x2-pcie-phy
181 - qcom,x1e80100-qmp-gen4x4-pcie-phy
182 - qcom,x1e80100-qmp-gen4x8-pcie-phy
187 clock-names:
190 - if:
195 - qcom,sa8775p-qmp-gen4x2-pcie-phy
196 - qcom,sa8775p-qmp-gen4x4-pcie-phy
201 clock-names:
204 - if:
209 - qcom,sm8550-qmp-gen4x2-pcie-phy
210 - qcom,sm8650-qmp-gen4x2-pcie-phy
211 - qcom,x1e80100-qmp-gen4x2-pcie-phy
212 - qcom,x1e80100-qmp-gen4x4-pcie-phy
213 - qcom,x1e80100-qmp-gen4x8-pcie-phy
218 reset-names:
224 reset-names:
227 - if:
232 - qcom,sm8450-qmp-gen4x2-pcie-phy
233 - qcom,sm8550-qmp-gen4x2-pcie-phy
234 - qcom,sm8650-qmp-gen4x2-pcie-phy
237 "#clock-cells":
241 "#clock-cells":
245 - |
246 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
248 pcie2b_phy: phy@1c18000 {
249 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
258 clock-names = "aux", "cfg_ahb", "ref", "rchng",
261 power-domains = <&gcc PCIE_2B_GDSC>;
264 reset-names = "phy";
266 vdda-phy-supply = <&vreg_l6d>;
267 vdda-pll-supply = <&vreg_l4d>;
269 #clock-cells = <0>;
270 clock-output-names = "pcie_2b_pipe_clk";
272 #phy-cells = <0>;
275 pcie2a_phy: phy@1c24000 {
276 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
285 clock-names = "aux", "cfg_ahb", "ref", "rchng",
288 power-domains = <&gcc PCIE_2A_GDSC>;
291 reset-names = "phy";
293 vdda-phy-supply = <&vreg_l6d>;
294 vdda-pll-supply = <&vreg_l4d>;
296 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
298 #clock-cells = <0>;
299 clock-output-names = "pcie_2a_pipe_clk";
301 #phy-cells = <0>;