Lines Matching +full:phy +full:- +full:names
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
10 - Vinod Koul <[email protected]>
13 QMP PHY controller supports physical layer functionality for a number of
19 - enum:
20 - qcom,ipq6018-qmp-pcie-phy
21 - qcom,ipq8074-qmp-gen3-pcie-phy
22 - qcom,ipq8074-qmp-pcie-phy
23 - qcom,ipq9574-qmp-gen3x1-pcie-phy
24 - qcom,ipq9574-qmp-gen3x2-pcie-phy
25 - items:
26 - enum:
27 - qcom,ipq5424-qmp-gen3x1-pcie-phy
28 - const: qcom,ipq9574-qmp-gen3x1-pcie-phy
29 - items:
30 - enum:
31 - qcom,ipq5424-qmp-gen3x2-pcie-phy
32 - const: qcom,ipq9574-qmp-gen3x2-pcie-phy
36 - description: serdes
41 clock-names:
43 - const: aux
44 - const: cfg_ahb
45 - const: pipe
50 reset-names:
52 - const: phy
53 - const: common
55 "#clock-cells":
58 clock-output-names:
61 "#phy-cells":
65 - compatible
66 - reg
67 - clocks
68 - clock-names
69 - resets
70 - reset-names
71 - "#clock-cells"
72 - clock-output-names
73 - "#phy-cells"
78 - |
79 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
80 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
82 phy@84000 {
83 compatible = "qcom,ipq6018-qmp-pcie-phy";
89 clock-names = "aux",
93 clock-output-names = "gcc_pcie0_pipe_clk_src";
94 #clock-cells = <0>;
96 #phy-cells = <0>;
100 reset-names = "phy",