Lines Matching +full:interrupt +full:- +full:names
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <[email protected]>
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
28 +-+-+-+-+-+-+-+-+
31 +-------+ +------+ +-----------+
33 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
35 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
44 to generate interrupt.
49 - items:
50 - enum:
51 - mediatek,mt7986-pcie
52 - mediatek,mt8188-pcie
53 - mediatek,mt8195-pcie
54 - const: mediatek,mt8192-pcie
55 - const: mediatek,mt8192-pcie
56 - const: airoha,en7581-pcie
61 reg-names:
63 - const: pcie-mac
72 iommu-map:
75 iommu-map-mask:
82 reset-names:
86 enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
92 clock-names:
96 assigned-clocks:
99 assigned-clock-parents:
105 phy-names:
107 - const: pcie-phy
109 power-domains:
112 '#interrupt-cells':
115 interrupt-controller:
116 description: Interrupt controller node for handling legacy PCI interrupts.
119 '#address-cells':
121 '#interrupt-cells':
123 interrupt-controller: true
126 - '#address-cells'
127 - '#interrupt-cells'
128 - interrupt-controller
133 - compatible
134 - reg
135 - reg-names
136 - interrupts
137 - ranges
138 - clocks
139 - clock-names
140 - '#interrupt-cells'
141 - interrupt-controller
144 - $ref: /schemas/pci/pci-host-bridge.yaml#
145 - if:
148 const: mediatek,mt8192-pcie
154 clock-names:
156 - const: pl_250m
157 - const: tl_26m
158 - const: tl_96m
159 - const: tl_32k
160 - const: peri_26m
161 - const: top_133m
167 reset-names:
171 - if:
176 - mediatek,mt8188-pcie
177 - mediatek,mt8195-pcie
183 clock-names:
185 - const: pl_250m
186 - const: tl_26m
187 - const: tl_96m
188 - const: tl_32k
189 - const: peri_26m
190 - const: peri_mem
196 reset-names:
200 - if:
205 - mediatek,mt7986-pcie
212 clock-names:
214 - const: pl_250m
215 - const: tl_26m
216 - const: peri_26m
217 - const: top_133m
223 reset-names:
227 - if:
230 const: airoha,en7581-pcie
236 clock-names:
238 - const: sys-ck
243 reset-names:
245 - const: phy-lane0
246 - const: phy-lane1
247 - const: phy-lane2
252 - |
253 #include <dt-bindings/interrupt-controller/arm-gic.h>
254 #include <dt-bindings/interrupt-controller/irq.h>
257 #address-cells = <2>;
258 #size-cells = <2>;
261 compatible = "mediatek,mt8192-pcie";
263 #address-cells = <3>;
264 #size-cells = <2>;
266 reg-names = "pcie-mac";
268 bus-range = <0x00 0xff>;
277 clock-names = "pl_250m", "tl_26m", "tl_96m",
279 assigned-clocks = <&topckgen 50>;
280 assigned-clock-parents = <&topckgen 91>;
283 phy-names = "pcie-phy";
287 reset-names = "phy", "mac";
289 #interrupt-cells = <1>;
290 interrupt-map-mask = <0 0 0 0x7>;
291 interrupt-map = <0 0 0 1 &pcie_intc 0>,
295 pcie_intc: interrupt-controller {
296 #address-cells = <0>;
297 #interrupt-cells = <1>;
298 interrupt-controller;