Lines Matching full:delay

36   # They are used to delay the data valid window, and align the window to
37   # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
40   cdns,phy-input-delay-sd-highspeed:
41     description: Value of the delay in the input path for SD high-speed timing
46   cdns,phy-input-delay-legacy:
47     description: Value of the delay in the input path for legacy timing
52   cdns,phy-input-delay-sd-uhs-sdr12:
53     description: Value of the delay in the input path for SD UHS SDR12 timing
58   cdns,phy-input-delay-sd-uhs-sdr25:
59     description: Value of the delay in the input path for SD UHS SDR25 timing
64   cdns,phy-input-delay-sd-uhs-sdr50:
65     description: Value of the delay in the input path for SD UHS SDR50 timing
70   cdns,phy-input-delay-sd-uhs-ddr50:
71     description: Value of the delay in the input path for SD UHS DDR50 timing
76   cdns,phy-input-delay-mmc-highspeed:
77     description: Value of the delay in the input path for MMC high-speed timing
82   cdns,phy-input-delay-mmc-ddr:
83     description: Value of the delay in the input path for eMMC high-speed DDR timing
86   # Each delay property represents the fraction of the clock period.
87   # The approximate delay value will be
88   # (<delay property value>/128)*sdmclk_clock_period.
93   cdns,phy-dll-delay-sdclk:
95       Value of the delay introduced on the sdclk output for all modes except
101   cdns,phy-dll-delay-sdclk-hsmmc:
103       Value of the delay introduced on the sdclk output for HS200, HS400 and
109   cdns,phy-dll-delay-strobe:
111       Value of the delay introduced on the dat_strobe input used in
156         cdns,phy-dll-delay-sdclk = <0>;