Lines Matching +full:bank +full:- +full:width
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <[email protected]>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
34 Reflects the memory layout with four integer values per bank. Format:
35 <bank-number> 0 <parent address of bank> <size>
39 "^.*@[0-3],[a-f0-9]+$":
46 of the relevant SROM bank.
51 Bank number, base address (relative to start of the bank) and size
53 typically 0 as this is the start of the bank.
56 reg-io-width:
59 Data width in bytes (1 or 2). If omitted, default of 1 is used.
61 samsung,srom-page-mode:
67 samsung,srom-timing:
68 $ref: /schemas/types.yaml#/definitions/uint32-array
72 Array of 6 integers, specifying bank timings in the following order:
76 Tacp: Page mode access cycle at Page mode (0 - 15)
77 Tcah: Address holding time after CSn (0 - 15)
78 Tcoh: Chip selection hold on OEn (0 - 15)
79 Tacc: Access cycle (0 - 31, the actual time is N + 1)
80 Tcos: Chip selection set-up before OEn (0 - 15)
81 Tacs: Address set-up before CSn (0 - 15)
84 - reg
85 - samsung,srom-timing
88 - compatible
89 - reg
94 - |
96 memory-controller@12560000 {
97 compatible = "samsung,exynos4210-srom";
101 - |
102 // Example: SROMc with SMSC911x ethernet chip on bank 3
103 memory-controller@12570000 {
104 #address-cells = <2>;
105 #size-cells = <1>;
111 compatible = "samsung,exynos4210-srom";
116 reg = <3 0 0x10000>; // Bank 3, offset = 0
117 phy-mode = "mii";
118 interrupt-parent = <&gpx0>;
120 reg-io-width = <2>;
121 smsc,irq-push-pull;
122 smsc,force-internal-phy;
124 samsung,srom-page-mode;
125 samsung,srom-timing = <9 12 1 9 1 1>;