Lines Matching +full:non +full:- +full:identical
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <[email protected]>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
17 It supports identical translation table format to the RISC-V address
19 Hardware uses in-memory command and fault reporting queues with wired
22 Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
24 For information on assigning RISC-V IOMMU to its peripheral devices,
30 # Since PCI provides built-in identification methods, compatible is not
31 # actually required. For non-PCIe hardware implementations 'riscv,iommu'
35 - items:
36 - enum:
37 - qemu,riscv-iommu
38 - const: riscv,iommu
39 - items:
40 - enum:
41 - pci1efd,edf1
42 - const: riscv,pci-iommu
47 For non-PCI devices this represents base address and size of for the
52 '#iommu-cells':
62 Wired interrupt vectors available for RISC-V IOMMU to notify the
63 RISC-V HARTS. The cause to interrupt vector is software defined
66 msi-parent: true
68 power-domains:
72 - compatible
73 - reg
74 - '#iommu-cells'
79 - |+
81 #include <dt-bindings/interrupt-controller/irq.h>
84 compatible = "qemu,riscv-iommu", "riscv,iommu";
86 interrupt-parent = <&aplic_smode>;
91 #iommu-cells = <1>;
99 - |+
101 #include <dt-bindings/interrupt-controller/irq.h>
104 compatible = "qemu,riscv-iommu", "riscv,iommu";
106 interrupt-parent = <&aplic_smode>;
108 #iommu-cells = <1>;
111 - |+
114 compatible = "qemu,riscv-iommu", "riscv,iommu";
116 msi-parent = <&imsics_smode>;
117 #iommu-cells = <1>;
120 - |+
123 #address-cells = <2>;
124 #size-cells = <2>;
128 #address-cells = <3>;
129 #size-cells = <2>;
137 iommu-map = <0x0 &iommu0 0x0 0x8>,
142 compatible = "pci1efd,edf1", "riscv,pci-iommu";
144 #iommu-cells = <1>;