Lines Matching +full:access +full:- +full:controller +full:- +full:names
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <[email protected]>
11 - Robin Murphy <[email protected]>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
37 - enum:
38 - qcom,qcm2290-smmu-500
39 - qcom,qcs615-smmu-500
40 - qcom,qcs8300-smmu-500
41 - qcom,qdu1000-smmu-500
42 - qcom,sa8255p-smmu-500
43 - qcom,sa8775p-smmu-500
44 - qcom,sar2130p-smmu-500
45 - qcom,sc7180-smmu-500
46 - qcom,sc7280-smmu-500
47 - qcom,sc8180x-smmu-500
48 - qcom,sc8280xp-smmu-500
49 - qcom,sdm670-smmu-500
50 - qcom,sdm845-smmu-500
51 - qcom,sdx55-smmu-500
52 - qcom,sdx65-smmu-500
53 - qcom,sdx75-smmu-500
54 - qcom,sm6115-smmu-500
55 - qcom,sm6125-smmu-500
56 - qcom,sm6350-smmu-500
57 - qcom,sm6375-smmu-500
58 - qcom,sm8150-smmu-500
59 - qcom,sm8250-smmu-500
60 - qcom,sm8350-smmu-500
61 - qcom,sm8450-smmu-500
62 - qcom,sm8550-smmu-500
63 - qcom,sm8650-smmu-500
64 - qcom,sm8750-smmu-500
65 - qcom,x1e80100-smmu-500
66 - const: qcom,smmu-500
67 - const: arm,mmu-500
69 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
73 - enum:
74 - qcom,qcm2290-smmu-500
75 - qcom,sc7180-smmu-500
76 - qcom,sc7280-smmu-500
77 - qcom,sc8180x-smmu-500
78 - qcom,sc8280xp-smmu-500
79 - qcom,sdm845-smmu-500
80 - qcom,sm6115-smmu-500
81 - qcom,sm6350-smmu-500
82 - qcom,sm6375-smmu-500
83 - qcom,sm8150-smmu-500
84 - qcom,sm8250-smmu-500
85 - qcom,sm8350-smmu-500
86 - qcom,sm8450-smmu-500
87 - const: arm,mmu-500
88 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
90 - enum:
91 - qcom,qcm2290-smmu-500
92 - qcom,qcs615-smmu-500
93 - qcom,sa8255p-smmu-500
94 - qcom,sa8775p-smmu-500
95 - qcom,sar2130p-smmu-500
96 - qcom,sc7280-smmu-500
97 - qcom,sc8180x-smmu-500
98 - qcom,sc8280xp-smmu-500
99 - qcom,sm6115-smmu-500
100 - qcom,sm6125-smmu-500
101 - qcom,sm8150-smmu-500
102 - qcom,sm8250-smmu-500
103 - qcom,sm8350-smmu-500
104 - qcom,sm8450-smmu-500
105 - qcom,sm8550-smmu-500
106 - qcom,sm8650-smmu-500
107 - qcom,sm8750-smmu-500
108 - qcom,x1e80100-smmu-500
109 - const: qcom,adreno-smmu
110 - const: qcom,smmu-500
111 - const: arm,mmu-500
112 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
116 - enum:
117 - qcom,sc7280-smmu-500
118 - qcom,sm8150-smmu-500
119 - qcom,sm8250-smmu-500
120 - const: qcom,adreno-smmu
121 - const: arm,mmu-500
122 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
124 - enum:
125 - qcom,msm8996-smmu-v2
126 - qcom,sc7180-smmu-v2
127 - qcom,sdm630-smmu-v2
128 - qcom,sdm670-smmu-v2
129 - qcom,sdm845-smmu-v2
130 - qcom,sm6350-smmu-v2
131 - qcom,sm7150-smmu-v2
132 - const: qcom,adreno-smmu
133 - const: qcom,smmu-v2
134 - description: Qcom Adreno GPUs on Google Cheza platform
136 - const: qcom,sdm845-smmu-v2
137 - const: qcom,smmu-v2
138 - description: Marvell SoCs implementing "arm,mmu-500"
140 - const: marvell,ap806-smmu-500
141 - const: arm,mmu-500
142 - description: NVIDIA SoCs that require memory controller interaction
143 and may program multiple ARM MMU-500s identically with the memory
144 controller interleaving translations between multiple instances
147 - enum:
148 - nvidia,tegra186-smmu
149 - nvidia,tegra194-smmu
150 - nvidia,tegra234-smmu
151 - const: nvidia,smmu-500
152 - items:
153 - const: arm,mmu-500
154 - const: arm,smmu-v2
155 - items:
156 - enum:
157 - arm,mmu-400
158 - arm,mmu-401
159 - const: arm,smmu-v1
160 - enum:
161 - arm,smmu-v1
162 - arm,smmu-v2
163 - arm,mmu-400
164 - arm,mmu-401
165 - arm,mmu-500
166 - cavium,smmu-v2
172 '#global-interrupts':
176 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
178 '#iommu-cells':
194 Interrupt list, with the first #global-interrupts entries corresponding to
202 dma-coherent:
210 calxeda,smmu-secure-config-access:
214 access to SMMU configuration registers. In this case non-secure aliases of
217 stream-match-mask:
220 For SMMUs supporting stream matching and using #iommu-cells = <1>,
224 Stream ID (e.g. for certain MMU-500 configurations given globally unique
226 using stream matching with #iommu-cells = <2>, and may be ignored if
229 clock-names:
237 power-domains:
241 nvidia,memory-controller:
243 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
244 The memory controller needs to be programmed with a mapping of memory
253 - compatible
254 - reg
255 - '#global-interrupts'
256 - '#iommu-cells'
257 - interrupts
262 - if:
267 - nvidia,tegra186-smmu
268 - nvidia,tegra194-smmu
269 - nvidia,tegra234-smmu
276 # The reference to the memory controller is required to ensure that the
280 - nvidia,memory-controller
286 - if:
291 - qcom,msm8998-smmu-v2
292 - qcom,sdm630-smmu-v2
295 - properties:
296 clock-names:
298 - const: bus
301 - description: bus clock required for downstream bus access and for
303 - properties:
304 clock-names:
306 - const: iface
307 - const: mem
308 - const: mem_iface
311 - description: interface clock required to access smmu's registers
313 - description: bus clock required for memory access
314 - description: bus clock required for GPU memory access
315 - properties:
316 clock-names:
318 - const: iface-mm
319 - const: iface-smmu
320 - const: bus-smmu
323 - description: interface clock required to access mnoc's registers
325 - description: interface clock required to access smmu's registers
327 - description: bus clock required for the smmu ptw
329 - if:
334 - qcom,sm6375-smmu-v2
337 - properties:
338 clock-names:
340 - const: bus
343 - description: bus clock required for downstream bus access and for
345 - properties:
346 clock-names:
348 - const: iface
349 - const: mem
350 - const: mem_iface
353 - description: interface clock required to access smmu's registers
355 - description: bus clock required for memory access
356 - description: bus clock required for GPU memory access
357 - properties:
358 clock-names:
360 - const: iface-mm
361 - const: iface-smmu
362 - const: bus-mm
363 - const: bus-smmu
366 - description: interface clock required to access mnoc's registers
368 - description: interface clock required to access smmu's registers
370 - description: bus clock required for downstream bus access
371 - description: bus clock required for the smmu ptw
373 - if:
378 - qcom,msm8996-smmu-v2
379 - qcom,sc7180-smmu-v2
380 - qcom,sdm845-smmu-v2
383 clock-names:
385 - const: bus
386 - const: iface
390 - description: bus clock required for downstream bus access and for
392 - description: interface clock required to access smmu's registers
395 - if:
400 - qcom,sa8775p-smmu-500
401 - qcom,sc7280-smmu-500
402 - qcom,sc8280xp-smmu-500
405 clock-names:
407 - const: gcc_gpu_memnoc_gfx_clk
408 - const: gcc_gpu_snoc_dvm_gfx_clk
409 - const: gpu_cc_ahb_clk
410 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
411 - const: gpu_cc_cx_gmu_clk
412 - const: gpu_cc_hub_cx_int_clk
413 - const: gpu_cc_hub_aon_clk
417 - description: GPU memnoc_gfx clock
418 - description: GPU snoc_dvm_gfx clock
419 - description: GPU ahb clock
420 - description: GPU hlos1_vote_GPU smmu clock
421 - description: GPU cx_gmu clock
422 - description: GPU hub_cx_int clock
423 - description: GPU hub_aon clock
425 - if:
430 - qcom,sc8180x-smmu-500
431 - qcom,sm6350-smmu-v2
432 - qcom,sm7150-smmu-v2
433 - qcom,sm8150-smmu-500
434 - qcom,sm8250-smmu-500
437 clock-names:
439 - const: ahb
440 - const: bus
441 - const: iface
445 - description: bus clock required for AHB bus access
446 - description: bus clock required for downstream bus access and for
448 - description: interface clock required to access smmu's registers
451 - if:
455 - enum:
456 - qcom,sm8350-smmu-500
457 - const: qcom,adreno-smmu
458 - const: qcom,smmu-500
459 - const: arm,mmu-500
462 clock-names:
464 - const: bus
465 - const: iface
466 - const: ahb
467 - const: hlos1_vote_gpu_smmu
468 - const: cx_gmu
469 - const: hub_cx_int
470 - const: hub_aon
475 - if:
479 - enum:
480 - qcom,qcm2290-smmu-500
481 - qcom,qcs615-smmu-500
482 - qcom,sm6115-smmu-500
483 - qcom,sm6125-smmu-500
484 - const: qcom,adreno-smmu
485 - const: qcom,smmu-500
486 - const: arm,mmu-500
489 clock-names:
491 - const: mem
492 - const: hlos
493 - const: iface
497 - description: GPU memory bus clock
498 - description: Voter clock required for HLOS SMMU access
499 - description: Interface clock required for register access
501 - if:
505 - const: qcom,sm8450-smmu-500
506 - const: qcom,adreno-smmu
507 - const: qcom,smmu-500
508 - const: arm,mmu-500
512 clock-names:
514 - const: gmu
515 - const: hub
516 - const: hlos
517 - const: bus
518 - const: iface
519 - const: ahb
523 - description: GMU clock
524 - description: GPU HUB clock
525 - description: HLOS vote clock
526 - description: GPU memory bus clock
527 - description: GPU SNoC bus clock
528 - description: GPU AHB clock
530 - if:
534 - enum:
535 - qcom,sar2130p-smmu-500
536 - qcom,sm8550-smmu-500
537 - qcom,sm8650-smmu-500
538 - qcom,x1e80100-smmu-500
539 - const: qcom,adreno-smmu
540 - const: qcom,smmu-500
541 - const: arm,mmu-500
544 clock-names:
546 - const: hlos
547 - const: bus
548 - const: iface
549 - const: ahb
553 - description: HLOS vote clock
554 - description: GPU memory bus clock
555 - description: GPU SNoC bus clock
556 - description: GPU AHB clock
558 - if:
562 - const: qcom,sm8750-smmu-500
563 - const: qcom,adreno-smmu
564 - const: qcom,smmu-500
565 - const: arm,mmu-500
568 clock-names:
570 - const: hlos
573 - description: HLOS vote clock
576 - if:
581 - cavium,smmu-v2
582 - marvell,ap806-smmu-500
583 - nvidia,smmu-500
584 - qcom,qcs8300-smmu-500
585 - qcom,qdu1000-smmu-500
586 - qcom,sa8255p-smmu-500
587 - qcom,sc7180-smmu-500
588 - qcom,sdm670-smmu-500
589 - qcom,sdm845-smmu-500
590 - qcom,sdx55-smmu-500
591 - qcom,sdx65-smmu-500
592 - qcom,sm6350-smmu-500
593 - qcom,sm6375-smmu-500
596 clock-names: false
599 - if:
603 const: qcom,sm6375-smmu-500
606 power-domains:
608 - description: SNoC MMU TBU RT GDSC
609 - description: SNoC MMU TBU NRT GDSC
610 - description: SNoC TURING MMU TBU0 GDSC
613 - power-domains
616 power-domains:
620 - |+
623 compatible = "arm,smmu-v1";
625 #global-interrupts = <2>;
632 #iommu-cells = <1>;
644 compatible = "arm,smmu-v1";
646 #global-interrupts = <2>;
653 #iommu-cells = <2>;
668 /* ARM MMU-500 with 10-bit stream ID input configuration */
670 compatible = "arm,mmu-500", "arm,smmu-v2";
672 #global-interrupts = <2>;
679 #iommu-cells = <1>;
680 /* always ignore appended 5-bit TBU number */
681 stream-match-mask = <0x7c00>;
685 /* bus whose child devices emit one unique 10-bit stream
687 iommu-map = <0 &smmu3 0 0x400>;
692 - |+
693 /* Qcom's arm,smmu-v2 implementation */
694 #include <dt-bindings/interrupt-controller/arm-gic.h>
695 #include <dt-bindings/interrupt-controller/irq.h>
697 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
700 #global-interrupts = <1>;
704 #iommu-cells = <1>;
705 power-domains = <&mmcc 0>;
709 clock-names = "bus", "iface";