Lines Matching +full:access +full:- +full:controller +full:- +full:names
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
15 controller. This binding document applies to both controllers. The register
20 The Tegra186 GPIO controller allows software to set the IO direction of,
22 to package balls is under the control of a separate pin controller hardware
25 a) Security registers, which allow configuration of allowed access to the
30 Access to this set of registers is not necessary in all circumstances.
31 Code that wishes to configure access to the GPIO registers needs access
33 GPIO data does not need access to these registers.
37 aliases" in address space, each of which access the same underlying
39 GPIO client is expected to access just one of these physical aliases.
47 The number of ports implemented by each GPIO controller varies. The number
49 controller are grouped and laid out according to the port they affect.
51 The mapping from port name to the GPIO controller that implements that
53 controller, are both extremely non-linear. The header file
54 <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
56 The values chosen for the names are alphabetically sorted within a
57 particular controller. Drivers need to map between the DT GPIO IDs and HW
60 Each GPIO controller can generate a number of interrupt signals. Each
62 ports. Thus, the number of interrupt signals generated by a controller
64 that the HW documentation refers to both the overall controller HW
65 module and the sets-of-ports as "controllers".
67 Each GPIO controller in fact generates multiple interrupts signals for
69 one of the interrupt signals generated by a set-of-ports. The intent is
72 The status of each of these per-port-set signals is reported via a
82 - nvidia,tegra186-gpio
83 - nvidia,tegra186-gpio-aon
84 - nvidia,tegra194-gpio
85 - nvidia,tegra194-gpio-aon
86 - nvidia,tegra234-gpio
87 - nvidia,tegra234-gpio-aon
89 reg-names:
91 - const: security
92 - const: gpio
97 - description: Security configuration registers.
98 - description: |
102 b) All physical aliases that exist in the controller. This is
112 gpio-controller: true
114 "#gpio-cells":
119 - The first cell is the pin number.
120 See <dt-bindings/gpio/tegra186-gpio.h>.
121 - The second cell contains flags:
122 - Bit 0 specifies polarity
123 - 0: Active-high (normal).
124 - 1: Active-low (inverted).
127 interrupt-controller: true
129 "#interrupt-cells":
134 - The first cell is the GPIO number.
135 See <dt-bindings/gpio/tegra186-gpio.h>.
136 - The second cell is contains flags:
137 - Bits [3:0] indicate trigger type and level:
138 - 1: Low-to-high edge triggered.
139 - 2: High-to-low edge triggered.
140 - 4: Active high level-sensitive.
141 - 8: Active low level-sensitive.
147 - if:
152 - nvidia,tegra186-gpio
153 - nvidia,tegra194-gpio
154 - nvidia,tegra234-gpio
161 - if:
166 - nvidia,tegra186-gpio-aon
167 - nvidia,tegra194-gpio-aon
168 - nvidia,tegra234-gpio-aon
176 - compatible
177 - reg
178 - reg-names
179 - interrupts
184 - |
185 #include <dt-bindings/interrupt-controller/irq.h>
188 compatible = "nvidia,tegra186-gpio";
189 reg-names = "security", "gpio";
198 gpio-controller;
199 #gpio-cells = <2>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
205 compatible = "nvidia,tegra186-gpio-aon";
206 reg-names = "security", "gpio";
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <2>;