Lines Matching +full:dma +full:- +full:channels
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 title: Texas Instruments K3 NAVSS Unified DMA
12 - Peter Ujfalusi <[email protected]>
15 The UDMA-P is intended to perform similar (but significantly upgraded)
16 functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
18 The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
21 Multiple Tx and Rx channels are provided within the DMA which allow multiple
22 segmentation or reassembly operations to be ongoing. The DMA controller
23 maintains state information for each of the channels which allows packet
25 channels in order to share the underlying DMA hardware. An external DMA
28 is indirectly controlled by the order in which blocks are pushed into the DMA
29 on the Rx PSI-L interface.
31 The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
32 channels. Channels in the UDMA-P can be configured to be either Packet-Based
33 or Third-Party channels on a channel by channel basis.
35 All transfers within NAVSS is done between PSI-L source and destination
37 The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
38 legacy, non PSI-L native peripherals. In the later case a special, small PDMA
39 is tasked to act as a bridge between the PSI-L fabric and the legacy
46 - $ref: ../dma-controller.yaml#
47 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
50 "#dma-cells":
54 The cell is the PSI-L thread ID of the remote (to UDMAP) end.
56 for source thread IDs (rx): 0 - 0x7fff
57 for destination thread IDs (tx): 0x8000 - 0xffff
59 Please refer to the device documentation for the PSI-L thread map and also
60 the PSI-L peripheral chapter for the correct thread ID.
62 When #dma-cells is 2, the second parameter is the channel ATYPE.
66 - ti,am654-navss-main-udmap
67 - ti,am654-navss-mcu-udmap
68 - ti,j721e-navss-main-udmap
69 - ti,j721e-navss-mcu-udmap
74 - description: UDMA-P Control /Status Registers region
75 - description: RX Channel Realtime Registers region
76 - description: TX Channel Realtime Registers region
77 - description: TX Configuration Registers region
78 - description: RX Configuration Registers region
79 - description: RX Flow Configuration Registers region
81 reg-names:
84 - const: gcfg
85 - const: rchanrt
86 - const: tchanrt
87 - const: tchan
88 - const: rchan
89 - const: rflow
91 msi-parent: true
97 ti,sci-rm-range-tchan:
101 $ref: /schemas/types.yaml#/definitions/uint32-array
106 ti,sci-rm-range-rchan:
110 $ref: /schemas/types.yaml#/definitions/uint32-array
115 ti,sci-rm-range-rflow:
119 $ref: /schemas/types.yaml#/definitions/uint32-array
125 - compatible
126 - "#dma-cells"
127 - reg
128 - reg-names
129 - msi-parent
130 - ti,sci
131 - ti,sci-dev-id
132 - ti,ringacc
133 - ti,sci-rm-range-tchan
134 - ti,sci-rm-range-rchan
135 - ti,sci-rm-range-rflow
139 "#dma-cells":
143 ti,udma-atype:
144 description: ATYPE value which should be used by non slave channels
148 - ti,udma-atype
153 - |+
155 #address-cells = <2>;
156 #size-cells = <2>;
159 compatible = "simple-mfd";
160 #address-cells = <2>;
161 #size-cells = <2>;
162 dma-coherent;
163 dma-ranges;
166 ti,sci-dev-id = <118>;
168 main_udmap: dma-controller@31150000 {
169 compatible = "ti,am654-navss-main-udmap";
176 reg-names = "gcfg", "rchanrt", "tchanrt", "tchan", "rchan", "rflow";
177 #dma-cells = <1>;
181 msi-parent = <&inta_main_udmass>;
184 ti,sci-dev-id = <188>;
186 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
188 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
190 ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */