Lines Matching full:transfer

72       The third cell is a 32-bit mask specifying the DMA transfer requirements:
77           0x0: port 0 is allocated to the source transfer
78           0x1: port 1 is allocated to the source transfer
83           0x0: port 0 is allocated to the destination transfer
84           0x1: port 1 is allocated to the destination transfer
91         -bit 12-13: The transfer complete event mode
92           0x0: at block level, transfer complete event is generated at the end
94           0x2: at LLI level, the transfer complete event is generated at the end
95                of the LLI transfer
97           0x3: at channel level, the transfer complete event is generated at the
104           0x1: prevent additional transfer to accommodate user constraints such as single transfer