Lines Matching +full:dma +full:- +full:names
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ DMA Controller
10 - Biju Das <[email protected]>
15 - enum:
16 - renesas,r7s72100-dmac # RZ/A1H
17 - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
18 - renesas,r9a07g044-dmac # RZ/G2{L,LC}
19 - renesas,r9a07g054-dmac # RZ/V2L
20 - renesas,r9a08g045-dmac # RZ/G3S
21 - const: renesas,rz-dmac
25 - description: Control and channel register block
26 - description: DMA extended resource selector block
31 interrupt-names:
33 - const: error
34 - const: ch0
35 - const: ch1
36 - const: ch2
37 - const: ch3
38 - const: ch4
39 - const: ch5
40 - const: ch6
41 - const: ch7
42 - const: ch8
43 - const: ch9
44 - const: ch10
45 - const: ch11
46 - const: ch12
47 - const: ch13
48 - const: ch14
49 - const: ch15
53 - description: DMA main clock
54 - description: DMA register access clock
56 clock-names:
58 - const: main
59 - const: register
61 '#dma-cells':
65 connected to the DMA client and the slave channel configuration
67 bits[0:9] - Specifies MID/RID value
68 bit[10] - Specifies DMA request high enable (HIEN)
69 bit[11] - Specifies DMA request detection type (LVL)
70 bits[12:14] - Specifies DMAACK output mode (AM)
71 bit[15] - Specifies Transfer Mode (TM)
73 dma-channels:
76 power-domains:
81 - description: Reset for DMA ARESETN reset terminal
82 - description: Reset for DMA RST_ASYNC reset terminal
84 reset-names:
86 - const: arst
87 - const: rst_async
90 - compatible
91 - reg
92 - interrupts
93 - interrupt-names
94 - '#dma-cells'
95 - dma-channels
98 - $ref: dma-controller.yaml#
100 - if:
106 - renesas,r7s72100-dmac
109 - clocks
110 - clock-names
111 - power-domains
112 - resets
113 - reset-names
118 - |
119 #include <dt-bindings/interrupt-controller/arm-gic.h>
120 #include <dt-bindings/clock/r9a07g044-cpg.h>
122 dmac: dma-controller@11820000 {
123 compatible = "renesas,r9a07g044-dmac",
124 "renesas,rz-dmac";
144 interrupt-names = "error",
151 clock-names = "main", "register";
152 power-domains = <&cpg>;
155 reset-names = "arst", "rst_async";
156 #dma-cells = <1>;
157 dma-channels = <16>;