Lines Matching +full:dma +full:- +full:names
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped registers. channels are split into two groups, called
12 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
16 - Peng Fan <[email protected]>
21 - enum:
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
24 - fsl,imx8qm-edma
25 - fsl,imx8ulp-edma
26 - fsl,imx93-edma3
27 - fsl,imx93-edma4
28 - fsl,imx95-edma5
29 - nxp,s32g2-edma
30 - items:
31 - const: fsl,ls1028a-edma
32 - const: fsl,vf610-edma
33 - items:
34 - const: nxp,s32g3-edma
35 - const: nxp,s32g2-edma
45 interrupt-names:
49 "#dma-cells":
51 Specifies the number of cells needed to encode an DMA channel.
54 cell 0: index of dma channel mux instance.
55 cell 1: peripheral dma request id.
58 cell 0: peripheral dma request id.
59 cell 1: dma channel priority.
60 cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h
62 - 2
63 - 3
65 dma-channels:
73 clock-names:
77 power-domains:
80 in ascending order according to their associated DMA channels.
84 big-endian:
91 - "#dma-cells"
92 - compatible
93 - reg
94 - interrupts
95 - dma-channels
98 - $ref: dma-controller.yaml#
99 - if:
104 - fsl,imx8qm-edma
105 - fsl,imx93-edma3
106 - fsl,imx93-edma4
107 - fsl,imx95-edma5
110 "#dma-cells":
114 # defined for the DMA channels.
115 interrupt-names: false
116 clock-names:
118 - const: dma
122 - if:
126 const: fsl,vf610-edma
132 clock-names:
134 - const: dmamux0
135 - const: dmamux1
139 interrupt-names:
141 - const: edma-tx
142 - const: edma-err
146 "#dma-cells":
148 dma-channels:
151 - if:
155 const: fsl,imx7ulp-edma
161 clock-names:
163 - const: dma
164 - const: dmamux0
171 "#dma-cells":
173 dma-channels:
176 - if:
180 const: fsl,imx8ulp-edma
185 clock-names:
189 - const: dma
190 - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$"
192 interrupt-names: false
195 "#dma-cells":
198 - if:
203 - fsl,vf610-edma
204 - fsl,imx7ulp-edma
205 - fsl,imx93-edma3
206 - fsl,imx93-edma4
207 - fsl,imx95-edma5
208 - fsl,imx8ulp-edma
209 - fsl,ls1028a-edma
212 - clocks
214 - if:
219 - fsl,imx8qm-adma
220 - fsl,imx8qm-edma
223 - power-domains
226 power-domains: false
228 - if:
232 const: nxp,s32g2-edma
238 clock-names:
240 - const: dmamux0
241 - const: dmamux1
245 interrupt-names:
247 - const: tx-0-15
248 - const: tx-16-31
249 - const: err
253 "#dma-cells":
255 dma-channels:
261 - |
262 #include <dt-bindings/interrupt-controller/arm-gic.h>
263 #include <dt-bindings/clock/vf610-clock.h>
265 edma0: dma-controller@40018000 {
266 #dma-cells = <2>;
267 compatible = "fsl,vf610-edma";
273 interrupt-names = "edma-tx", "edma-err";
274 dma-channels = <32>;
275 clock-names = "dmamux0", "dmamux1";
279 - |
280 #include <dt-bindings/interrupt-controller/arm-gic.h>
281 #include <dt-bindings/clock/imx7ulp-clock.h>
283 edma1: dma-controller@40080000 {
284 #dma-cells = <2>;
285 compatible = "fsl,imx7ulp-edma";
288 dma-channels = <32>;
305 /* last is eDMA2-ERR interrupt */
307 clock-names = "dma", "dmamux0";
311 - |
312 #include <dt-bindings/interrupt-controller/arm-gic.h>
313 #include <dt-bindings/firmware/imx/rsrc.h>
315 dma-controller@5a9f0000 {
316 compatible = "fsl,imx8qm-edma";
318 #dma-cells = <3>;
319 dma-channels = <8>;
328 power-domains = <&pd IMX_SC_R_DMA_3_CH0>,