Lines Matching +full:bus +full:- +full:width
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/adi,axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI-DMAC DMA controller
10 FPGA-based DMA controller designed for use with high-speed converter hardware.
15 - Nuno Sa <[email protected]>
21 const: adi,axi-dmac-1.00.a
32 "#dma-cells":
39 This sub-node must contain a sub-node for each DMA channel. This node is
45 "#size-cells":
47 "#address-cells":
51 "^dma-channel@[0-9a-f]+$":
54 DMA channel properties based on HDL compile-time configuration.
61 adi,source-bus-width:
63 description: Width of the source bus in bits.
66 adi,destination-bus-width:
68 description: Width of the destination bus in bits.
71 adi,source-bus-type:
74 Type of the source bus.
81 adi,destination-bus-type:
83 description: Type of the destination bus (see adi,source-bus-type).
86 adi,length-width:
89 description: Width of the DMA transfer length register.
104 - reg
105 - adi,source-bus-width
106 - adi,destination-bus-width
107 - adi,source-bus-type
108 - adi,destination-bus-type
111 - "#size-cells"
112 - "#address-cells"
115 - compatible
116 - reg
117 - interrupts
118 - clocks
119 - "#dma-cells"
122 - |
123 dma-controller@7c420000 {
124 compatible = "adi,axi-dmac-1.00.a";
128 #dma-cells = <1>;