Lines Matching +full:dt +full:- +full:bindings
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <[email protected]>
11 - Philipp Zabel <[email protected]>
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
24 - enum:
25 - mediatek,mt2701-disp-ovl
26 - mediatek,mt8173-disp-ovl
27 - mediatek,mt8183-disp-ovl
28 - mediatek,mt8192-disp-ovl
29 - mediatek,mt8195-disp-ovl
30 - mediatek,mt8195-mdp3-ovl
31 - items:
32 - enum:
33 - mediatek,mt7623-disp-ovl
34 - mediatek,mt2712-disp-ovl
35 - const: mediatek,mt2701-disp-ovl
36 - items:
37 - enum:
38 - mediatek,mt6795-disp-ovl
39 - const: mediatek,mt8173-disp-ovl
40 - items:
41 - enum:
42 - mediatek,mt8186-disp-ovl
43 - mediatek,mt8365-disp-ovl
44 - const: mediatek,mt8192-disp-ovl
45 - items:
46 - const: mediatek,mt8188-disp-ovl
47 - const: mediatek,mt8195-disp-ovl
48 - items:
49 - const: mediatek,mt8188-mdp3-ovl
50 - const: mediatek,mt8195-mdp3-ovl
58 power-domains:
59 description: A phandle and PM domain specifier as defined by bindings of
61 Documentation/devicetree/bindings/power/power-domain.yaml for details.
65 - description: OVL Clock
70 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
72 mediatek,gce-client-reg:
76 defined in the header include/dt-bindings/gce/<chip>-gce.h.
77 $ref: /schemas/types.yaml#/definitions/phandle-array
99 - port@0
100 - port@1
103 - compatible
104 - reg
105 - interrupts
106 - power-domains
107 - clocks
108 - iommus
113 - |
114 #include <dt-bindings/interrupt-controller/arm-gic.h>
115 #include <dt-bindings/clock/mt8173-clk.h>
116 #include <dt-bindings/power/mt8173-power.h>
117 #include <dt-bindings/gce/mt8173-gce.h>
118 #include <dt-bindings/memory/mt8173-larb-port.h>
121 #address-cells = <2>;
122 #size-cells = <2>;
125 compatible = "mediatek,mt8173-disp-ovl";
128 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
131 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;