Lines Matching +full:mipi +full:- +full:to +full:- +full:edp
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <[email protected]>
11 - Philipp Zabel <[email protected]>
12 - Jitao Shi <[email protected]>
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
20 - $ref: /schemas/display/dsi-controller.yaml#
25 - enum:
26 - mediatek,mt2701-dsi
27 - mediatek,mt7623-dsi
28 - mediatek,mt8167-dsi
29 - mediatek,mt8173-dsi
30 - mediatek,mt8183-dsi
31 - mediatek,mt8186-dsi
32 - mediatek,mt8188-dsi
33 - items:
34 - enum:
35 - mediatek,mt6795-dsi
36 - const: mediatek,mt8173-dsi
37 - items:
38 - enum:
39 - mediatek,mt8195-dsi
40 - mediatek,mt8365-dsi
41 - const: mediatek,mt8183-dsi
49 power-domains:
54 - description: Engine Clock
55 - description: Digital Clock
56 - description: HS Clock
58 clock-names:
60 - const: engine
61 - const: digital
62 - const: hs
70 phy-names:
72 - const: dphy
77 Output port node. This port should be connected to the input
78 port of an attached DSI panel or DSI-to-eDP encoder chip.
84 to either the primary, secondary, etc, display pipeline.
94 DSI output to an attached DSI panel, or a DSI-to-X encoder chip
97 - port@0
98 - port@1
101 - compatible
102 - reg
103 - interrupts
104 - power-domains
105 - clocks
106 - clock-names
107 - phys
108 - phy-names
111 - required:
112 - port
113 - required:
114 - ports
119 - |
120 #include <dt-bindings/clock/mt8183-clk.h>
121 #include <dt-bindings/interrupt-controller/arm-gic.h>
122 #include <dt-bindings/interrupt-controller/irq.h>
123 #include <dt-bindings/power/mt8183-power.h>
124 #include <dt-bindings/phy/phy.h>
125 #include <dt-bindings/reset/mt8183-resets.h>
128 #address-cells = <2>;
129 #size-cells = <2>;
132 compatible = "mediatek,mt8183-dsi";
135 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
139 clock-names = "engine", "digital", "hs";
142 phy-names = "dphy";
145 remote-endpoint = <&panel_in>;